Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 166kb
  • Downloaded :0次
  • Author :w***
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Introduction - If you have any usage issues, please Google them yourself
Odd frequency and frequency-doubling (just modify the parameters can be achieved relatively rare sub-base frequency and octave)
Packet file list
(Preview for download)
奇数分频和倍频(只需修改参数就可以实现较难得基数分频和倍频)
..........................................................\threediv_clk
..........................................................\............\db
..........................................................\............\..\threediv_clk.asm.qmsg
..........................................................\............\..\threediv_clk.cbx.xml
..........................................................\............\..\threediv_clk.cmp.cdb
..........................................................\............\..\threediv_clk.cmp.hdb
..........................................................\............\..\threediv_clk.cmp.kpt
..........................................................\............\..\threediv_clk.cmp.logdb
..........................................................\............\..\threediv_clk.cmp.rdb
..........................................................\............\..\threediv_clk.cmp.tdb
..........................................................\............\..\threediv_clk.cmp0.ddb
..........................................................\............\..\threediv_clk.dbp
..........................................................\............\..\threediv_clk.db_info
..........................................................\............\..\threediv_clk.eco.cdb
..........................................................\............\..\threediv_clk.eds_overflow
..........................................................\............\..\threediv_clk.fit.qmsg
..........................................................\............\..\threediv_clk.fnsim.cdb
..........................................................\............\..\threediv_clk.fnsim.hdb
..........................................................\............\..\threediv_clk.fnsim.qmsg
..........................................................\............\..\threediv_clk.hier_info
..........................................................\............\..\threediv_clk.hif
..........................................................\............\..\threediv_clk.map.cdb
..........................................................\............\..\threediv_clk.map.hdb
..........................................................\............\..\threediv_clk.map.logdb
..........................................................\............\..\threediv_clk.map.qmsg
..........................................................\............\..\threediv_clk.pre_map.cdb
..........................................................\............\..\threediv_clk.pre_map.hdb
..........................................................\............\..\threediv_clk.psp
..........................................................\............\..\threediv_clk.rtlv.hdb
..........................................................\............\..\threediv_clk.rtlv_sg.cdb
..........................................................\............\..\threediv_clk.rtlv_sg_swap.cdb
..........................................................\............\..\threediv_clk.sgdiff.cdb
..........................................................\............\..\threediv_clk.sgdiff.hdb
..........................................................\............\..\threediv_clk.signalprobe.cdb
..........................................................\............\..\threediv_clk.sim.hdb
..........................................................\............\..\threediv_clk.sim.qmsg
..........................................................\............\..\threediv_clk.sim.rdb
..........................................................\............\..\threediv_clk.sim.vwf
..........................................................\............\..\threediv_clk.sld_design_entry.sci
..........................................................\............\..\threediv_clk.sld_design_entry_dsc.sci
..........................................................\............\..\threediv_clk.syn_hier_info
..........................................................\....
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is the largest source code store in internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.