Based on CPLD/FPGA multiplier of 16 to achieve the VHDL

乘法器
......\db
......\..\add_sub_fjh.tdf
......\..\mul16.asm.qmsg
......\..\mul16.asm_labs.ddb
......\..\mul16.cbx.xml
......\..\mul16.cmp.cdb
......\..\mul16.cmp.hdb
......\..\mul16.cmp.logdb
......\..\mul16.cmp.rdb
......\..\mul16.cmp.tdb
......\..\mul16.cmp0.ddb
......\..\mul16.db_info
......\..\mul16.eco.cdb
......\..\mul16.eds_overflow
......\..\mul16.fit.qmsg
......\..\mul16.fnsim.cdb
......\..\mul16.fnsim.hdb
......\..\mul16.fnsim.qmsg
......\..\mul16.hier_info
......\..\mul16.hif
......\..\mul16.map.cdb
......\..\mul16.map.hdb
......\..\mul16.map.logdb
......\..\mul16.map.qmsg
......\..\mul16.pre_map.cdb
......\..\mul16.pre_map.hdb
......\..\mul16.rtlv.hdb
......\..\mul16.rtlv_sg.cdb
......\..\mul16.rtlv_sg_swap.cdb
......\..\mul16.sgdiff.cdb
......\..\mul16.sgdiff.hdb
......\..\mul16.signalprobe.cdb
......\..\mul16.sim.cvwf
......\..\mul16.sim.hdb
......\..\mul16.sim.qmsg
......\..\mul16.sim.rdb
......\..\mul16.simfam
......\..\mul16.sld_design_entry.sci
......\..\mul16.sld_design_entry_dsc.sci
......\..\mul16.syn_hier_info
......\..\mul16.tan.qmsg
......\..\mul16.tis_db_list.ddb
......\..\mul16.tmw_info
......\..\prev_cmp_mul16.asm.qmsg
......\..\prev_cmp_mul16.fit.qmsg
......\..\prev_cmp_mul16.map.qmsg
......\..\prev_cmp_mul16.qmsg
......\..\prev_cmp_mul16.sim.qmsg
......\..\prev_cmp_mul16.tan.qmsg
......\..\wed.wsf
......\mul16.asm.rpt
......\mul16.done
......\mul16.fit.rpt
......\mul16.fit.smsg
......\mul16.fit.summary
......\mul16.flow.rpt
......\mul16.map.rpt
......\mul16.map.summary
......\mul16.pin
......\mul16.pof
......\mul16.qpf
......\mul16.qsf
......\mul16.qws
......\mul16.sim.rpt
......\mul16.tan.rpt
......\mul16.tan.summary
......\mul16.vhd
......\mul16.vhd.bak
......\mul16.vwf

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