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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 26kb
  • Downloaded :0次
  • Author :金***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Fifo generic design, with a testbench, and design_flow
Packet file list
(Preview for download)
generic_fifos
.............\bench
.............\.....\CVS
.............\.....\...\Entries
.............\.....\...\Repository
.............\.....\...\Root
.............\.....\verilog
.............\.....\.......\CVS
.............\.....\.......\...\Entries
.............\.....\.......\...\Repository
.............\.....\.......\...\Root
.............\.....\.......\test_bench_top.v
.............\CVS
.............\...\Entries
.............\...\Repository
.............\...\Root
.............\doc
.............\...\CVS
.............\...\...\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\README.txt
.............\rtl
.............\...\CVS
.............\...\...\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\verilog
.............\...\.......\CVS
.............\...\.......\...\Entries
.............\...\.......\...\Repository
.............\...\.......\...\Root
.............\...\.......\generic_fifo_dc.v
.............\...\.......\generic_fifo_dc_gray.v
.............\...\.......\generic_fifo_lfsr.v
.............\...\.......\generic_fifo_sc_a.v
.............\...\.......\generic_fifo_sc_b.v
.............\...\.......\lfsr.v
.............\...\.......\timescale.v
.............\sim
.............\...\CVS
.............\...\...\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\rtl_sim
.............\...\.......\bin
.............\...\.......\...\CVS
.............\...\.......\...\...\Entries
.............\...\.......\...\...\Repository
.............\...\.......\...\...\Root
.............\...\.......\...\Makefile
.............\...\.......\CVS
.............\...\.......\...\Entries
.............\...\.......\...\Repository
.............\...\.......\...\Root
.............\...\.......\run
.............\...\.......\...\CVS
.............\...\.......\...\...\Entries
.............\...\.......\...\...\Repository
.............\...\.......\...\...\Root
.............\...\.......\...\waves
.............\...\.......\...\.....\CVS
.............\...\.......\...\.....\...\Entries
.............\...\.......\...\.....\...\Repository
.............\...\.......\...\.....\...\Root
.............\...\.......\...\.....\waves.do
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