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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 143kb
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  • Author :邵***
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Introduction - If you have any usage issues, please Google them yourself
VHDL multiplier four input four-output code design
Packet file list
(Preview for download)
Mul
...\cmp_state.ini
...\db
...\..\Mul.asm.qmsg
...\..\Mul.cmp.cdb
...\..\Mul.cmp.ddb
...\..\Mul.cmp.hdb
...\..\Mul.cmp.rdb
...\..\Mul.cmp.tdb
...\..\Mul.dat_manager.dat
...\..\Mul.db_info
...\..\Mul.fit.qmsg
...\..\Mul.hier_info
...\..\Mul.hif
...\..\Mul.icc
...\..\Mul.map.cdb
...\..\Mul.map.hdb
...\..\Mul.map.qmsg
...\..\Mul.pre_map.hdb
...\..\Mul.project.hdb
...\..\Mul.rtlv.hdb
...\..\Mul.rtlv_sg.cdb
...\..\Mul.rtlv_sg_swap.cdb
...\..\Mul.sgdiff.cdb
...\..\Mul.sgdiff.hdb
...\..\Mul.signalprobe.cdb
...\..\Mul.sim.hdb
...\..\Mul.sim.qmsg
...\..\Mul.sim.rdb
...\..\Mul.sim.vwf
...\..\Mul.sld_design_entry.sci
...\..\Mul.sld_design_entry_dsc.sci
...\..\Mul.syn_hier_info
...\..\Mul.tan.qmsg
...\..\Mul_cmp.qrpt
...\..\Mul_sim.qrpt
...\Mul.asm.rpt
...\Mul.done
...\Mul.fit.eqn
...\Mul.fit.rpt
...\Mul.fit.summary
...\Mul.flow.rpt
...\Mul.map.eqn
...\Mul.map.rpt
...\Mul.map.summary
...\Mul.pin
...\Mul.qpf
...\Mul.qsf
...\Mul.qws
...\Mul.sim.rpt
...\Mul.tan.rpt
...\Mul.tan.summary
...\Mul.vhd
...\Mul.vwf
...\sim.cfg
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