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61EDA_D1051

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 24kb
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  • Author :缺****
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Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
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用VHDL编写的计算器:能实现简单的加减乘除四则运算
................................................\calculator
................................................\..........\add.vhd
................................................\..........\add1.vhd
................................................\..........\div.vhd
................................................\..........\fadd.vhd
................................................\..........\fadd4.vhd
................................................\..........\key_ctrl.vhd
................................................\..........\mul.vhd
................................................\..........\mul2.vhd
................................................\..........\segment.vhd
................................................\..........\sign.vhd
................................................\..........\sub.vhd
................................................\..........\top.bit
................................................\..........\top.ucf
................................................\..........\top.vhd
................................................\使用说明请参看右侧注释====〉〉.txt
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