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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 407kb
  • Downloaded :0次
  • Author :王***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Can be time-conditioning, 12, 24 hours conversion, time, alarm clock
Packet file list
(Preview for download)
shiyan10
........\act.vhd
........\any_even.vhd
........\cmp_state.ini
........\db
........\..\add_sub_qch.tdf
........\..\watch.asm.qmsg
........\..\watch.cmp.cdb
........\..\watch.cmp.ddb
........\..\watch.cmp.hdb
........\..\watch.cmp.rdb
........\..\watch.cmp.tdb
........\..\watch.csf.qmsg
........\..\watch.db_info
........\..\watch.fit.qmsg
........\..\watch.hif
........\..\watch.map.cdb
........\..\watch.map.hdb
........\..\watch.map.qmsg
........\..\watch.pre_map.hdb
........\..\watch.project.hdb
........\..\watch.rtlv.hdb
........\..\watch.rtlv_sg.cdb
........\..\watch.rtlv_sg_swap.cdb
........\..\watch.sgdiff.cdb
........\..\watch.sgdiff.hdb
........\..\watch.tan.qmsg
........\..\watch.watch.sld_design_entry.sci
........\..\watch_cmp.qrpt
........\..\watch_hier_info
........\..\watch_syn_hier_info
........\minute.vhd
........\msecond.vhd
........\second.vhd
........\watch.asm.rpt
........\watch.cdf
........\watch.done
........\watch.fit.eqn
........\watch.fit.rpt
........\watch.flow.rpt
........\watch.map.eqn
........\watch.map.rpt
........\watch.pin
........\watch.pof
........\watch.qpf
........\watch.qsf
........\watch.qws
........\watch.sof
........\watch.tan.rpt
........\watch.tan.summary
........\watch.vhd
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