[DSP program] fft_dma

Description: Based on the Fourier Transform dskc5402 dma examples
Platform: | Size: 34816 | Author: 王煦 | Hits:

[DSP program] dsp1

Description: Speech Signal Denoising Based on TMS320C54X and coding system: voice signal u/A law hardware compression procedure to: TMS320C54X+ TLC320AD50 mainly to achieve
Platform: | Size: 1024 | Author: 李凌 | Hits:

[DSP program] dsp2

Description: Speech Signal Denoising Based on TMS320C54X and coding system: speech signal acquisition and playback hardware to the main program: TMS320C54X+ TLC320AD50 mainly to achieve
Platform: | Size: 2048 | Author: 李凌 | Hits:

[DSP program] dsp3

Description: Speech Signal Denoising Based on TMS320C54X and coding system: CVSD encoding the C language code to hardware: TMS320C54X+ TLC320AD50 mainly to achieve
Platform: | Size: 1024 | Author: 李凌 | Hits:

[DSP program] powerp

Description: On the power spectrum estimation, periodogram, since the relevant law, bartlett law and Welch law, there is a Complex Cepstrum estimated code
Platform: | Size: 1024 | Author: | Hits:

[DSP program] vga_color

Description: this a sample about the VGA COLORBAR, the function of this code is show eight different colour in VGA, it s default installation is D: RedLogicRCII_samples, and the software environment is quatrusII 5.0, it is usefull fo
Platform: | Size: 243712 | Author: 王明 | Hits:

[DSP program] vga_blue_pro

Description: this a sample about the VGA BLUE, the function of this code is show blue in VGA, it s default installation is D: RedLogicRCII_samples, and the software environment is quatrusII 5.0, it is usefull for studying hardware.
Platform: | Size: 221184 | Author: 王明 | Hits:

[DSP program] wash

Description: A program written in VHDL using VHDL procedures
Platform: | Size: 294912 | Author: wufeng | Hits:

[DSP program] one

Description: VHDL written by a NC sub-frequency procedures. In this case is divided into 1Hz to 64HZ
Platform: | Size: 121856 | Author: wufeng | Hits:

[DSP program] ten

Description: A very good VHDL procedures. 64HZ can be divided into 0.1Hz
Platform: | Size: 132096 | Author: wufeng | Hits:

[DSP program] twenty

Description: A very good VHDL program. 0.05HZ can be divided into 64HZ
Platform: | Size: 132096 | Author: wufeng | Hits:

[DSP program] counnt

Description: Use VHDL to write a countdown procedure
Platform: | Size: 155648 | Author: wufeng | Hits: