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VHDL-FPGA-Verilog list
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LCMV optimization design array signal processing, Very suitable for the study using computer vision, Using high-order cumulants of MPSK signal modulation recognition.
Update : 2025-01-11 Size : 7kb Publisher : pouliutangsai

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AD9361 IP core, used on Linux, Vivado2014.2.
Update : 2025-01-11 Size : 779kb Publisher : 小陈3

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AD9361 IP core, used on Windows, Vivado2014.2
Update : 2025-01-11 Size : 1.28mb Publisher : 小陈3

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AD9361 IP core, used on Linux, Vivado2015.2
Update : 2025-01-11 Size : 754kb Publisher : 小陈3

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AD9361 IP core, used on Windows, Vivado2015.2
Update : 2025-01-11 Size : 1.33mb Publisher : 小陈3

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AD9361 IP core, used on Linux, Vivado2015.2
Update : 2025-01-11 Size : 911kb Publisher : 小陈3

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AD9361 IP core, used on Windows, Vivado2016.2
Update : 2025-01-11 Size : 1.66mb Publisher : 小陈3

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Elevator - VHDL Project
Update : 2025-01-11 Size : 237kb Publisher : HotavioH

IIC configuration ov7670, images stored to SDRAM, and displayed through the VGA
Update : 2025-01-11 Size : 6.65mb Publisher : songchao

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The uart module with apb interface
Update : 2025-01-11 Size : 3kb Publisher : songchao

read bmp data to array ,used in video stream gen when sim
Update : 2025-01-11 Size : 2kb Publisher : stone%^_^

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Serial communication, support baud rate selection
Update : 2025-01-11 Size : 222kb Publisher : 疯狂の程序猿
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