VHDL-FPGA-Verilog List Page 188

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .83 .84 .85 .86 .87 188.89 .90 .91 .92 .93 ... 4311 »

MIL-STD-1553B代码 Downloaded：0: FPGA implementation of 1553B codec function, Verilog language
Update : 2025-01-11 Size : 141kb Publisher : 易小木
ps2 Downloaded：0: PS2 keyboard program, you can directly use, you can download, including the source file, you can use directly
Update : 2025-01-11 Size : 858kb Publisher : 偶买尬
ni677 Downloaded：0: Including principal component analysis, factor analysis, Bayesian analysis, Pisarenko harmonic decomposition algorithm, PV modules contain, MPPT module, BOOST module, inverter module.
Update : 2025-01-11 Size : 14kb Publisher : tanniefen
xjrsb Downloaded：0: Based on matlab GUI interface design, Complete class-based image processing, contains all of the source code, auto image, Related impulse response analysis algorithm and inspection.
Update : 2025-01-11 Size : 12kb Publisher : jienenfui
ndbwu Downloaded：0: Including script files and function files in the form, Clustering analysis based on Euclidean distance, Waveform data analysis.
Update : 2025-01-11 Size : 12kb Publisher : jienenfui
I2C Downloaded：0: I2C master, support a variety of baud rates, support arbitration.
Update : 2025-01-11 Size : 7kb Publisher : shuli198349
lcd Downloaded：0: LCD controller, including the initial and control modules, power automatically painted initial ram inside the image.
Update : 2025-01-11 Size : 8kb Publisher : shuli198349
jeday Downloaded：0: This is the second energy entropy matlab code, Signal Processing ESPRIT method, GSM is GMSK modulation signal generation.
Update : 2025-01-11 Size : 11kb Publisher : tougaofao
yui_dy42 Downloaded：0: Linear array using cut than learning laid upon the right control of the main sidelobe ratio, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. Using high-order cumulants of MPSK signal
Update : 2025-01-11 Size : 11kb Publisher : taomunlennen
I2Csalve.v Downloaded：0: Modified I2C salve design 1. Asynchronous design: ASIC or FPGA design option 2. 8 bits CSR RW interface: 0~15, address and control 3. PAD not included 4. Altera CPLD verified
Update : 2025-01-11 Size : 2kb Publisher : ph5077
超声波电源程序基础 Downloaded：0: The MSP430 microcontroller calculates the frequency control word, and then passes the control word to the DDS chip to synthesize the high frequency electrical signal
Update : 2025-01-11 Size : 2kb Publisher : 黄正辉
标准SDR SDRAM控制器参考设计，Lattice提供 Downloaded：0: Description: SDR SDRAM controller from lattice has been analyzed code available, we can refer to modify, to form their own examples
Update : 2025-01-11 Size : 17kb Publisher : modelsim

« 1 2 ... .83 .84 .85 .86 .87 188.89 .90 .91 .92 .93 ... 4311 »

Search in result