VHDL-FPGA-Verilog List Page 3185

VHDL-FPGA-Verilog list

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jianpanjiekoups2 Downloaded：0: 【Original】 44 matrix keyboard interface program (VHDL) (2009-10-27 201747) Tags: Matrix keyboard vhdl Zatan junior version: support the importation of three 10-digit addition and subtraction with two operands or compare
Update : 2025-04-22 Size : 3kb Publisher : hooyu
VHDLkejian Downloaded：0: EDA technology from a sense: to learn a software approach to efficiently complete the hardware design of computer technology __------ VHDL text description of the function of the system- the system logical description (a
Update : 2025-04-22 Size : 1.59mb Publisher : hooyu
divider Downloaded：0: Efficient VERIFLOG description language of the divider, than the average high speed
Update : 2025-04-22 Size : 139kb Publisher : henry
hdb3_decode Downloaded：0: hdb3 code encoding and decoding code, including modules.
Update : 2025-04-22 Size : 636kb Publisher : Gina
weitongbu Downloaded：0: failed to translate
Update : 2025-04-22 Size : 189kb Publisher : Gina
M Downloaded：0: Small M sequence generator. Sequence length is 7. Facilitate the change.
Update : 2025-04-22 Size : 101kb Publisher : Gina
eth Downloaded：1: Ahb a Gigabit Ethernet interface MAC, including the configuration interface apb
Update : 2025-04-22 Size : 31kb Publisher : daisy
traffic_light Downloaded：0: EDA courses compiled job- traffic lights, the specific requirement is that the crossroads on the road in both directions each with a group of red, green and yellow lights, indicating the order: One way is to green, yello
Update : 2025-04-22 Size : 275kb Publisher : buyi
BPSK_track_10.23M_BD_IF46.52MHz Downloaded：0: communications between DSP and FPGA Besides produce ahead code present code late code and correlation integral result
Update : 2025-04-22 Size : 3.17mb Publisher : laonong
VGA_Ctrl_VHDL Downloaded：0: The use of VHDL in the Quartus II environment to realize VGA interface display control, display monochrome screen, color bars, checkerboard grid and so on.
Update : 2025-04-22 Size : 601kb Publisher : nostalgia
dds_final Downloaded：1: Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
Update : 2025-04-22 Size : 1.56mb Publisher : nostalgia
OCIDEC_Drivers Downloaded：0: OCIDEC ATA driver source code
Update : 2025-04-22 Size : 11kb Publisher : 張又又

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