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VHDL-FPGA-Verilog list
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crc16 ,datawidth is 8,coding by verilog
Update : 2025-04-21 Size : 1kb Publisher : chenk

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crc32,datawidth is8,coding by verilog
Update : 2025-04-21 Size : 1kb Publisher : chenk

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crc_ccit, datawidth is 8,coding by verilog
Update : 2025-04-21 Size : 1kb Publisher : chenk

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ADC0809 based data acquisition system, for 0 ~ 5V voltage of the collection, display to the digital tube display
Update : 2025-04-21 Size : 1kb Publisher : liuyong

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UART communication program based on X3CS400 FPGA, develop enviroment: ISE7.0,completed by verilog。 The result could be seen on the Uart debug assitant.
Update : 2025-04-21 Size : 556kb Publisher : lingfeng

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======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below. . |-- doc - Documentation
Update : 2025-04-21 Size : 878kb Publisher : xuchao

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i need to refer and search for calculator verilog.hope i can find answer from it.
Update : 2025-04-21 Size : 47kb Publisher : Mei juan

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vhdl
Update : 2025-04-21 Size : 1.22mb Publisher : zhangjun

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ceu Verilog
Update : 2025-04-21 Size : 4kb Publisher : 方静

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ram modules, Verilog program implementation, there are a lot of words Yaoda
Update : 2025-04-21 Size : 232kb Publisher : 方静

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QuartusII detailed instructions, the steps detailed, easy to learn and easy to understand, is a PPT tutorial.
Update : 2025-04-21 Size : 827kb Publisher : huang

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VHDL, detailed instructions, easy access, along with a lot of the typical program code.
Update : 2025-04-21 Size : 38kb Publisher : huang
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