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VHDL-FPGA-Verilog list
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Details of the DDS principle, the document easy to understand, is a good choice for hardware developers ....
Date : 2025-08-12 Size : 444kb User : 刘历辉 -
sdram controller
Date : 2025-08-12 Size : 4kb User : 田云钧 -
Some of the use of logic synthesis, tips, do-chip front-end to have a good look
Date : 2025-08-12 Size : 627kb User : 舒马赫 -
FPGA-works, a more formal veilog code
Date : 2025-08-12 Size : 44.69mb User : jiaming -
Control Development Board VGA interface control above CRT monitors work 2. Part1 directory is the color of display 3. Part2 directory is a table tennis game show 4. Project \ project folder inside 5. The source file and
Date : 2025-08-12 Size : 1.2mb User : 一天 -
HDB3 encoder and decoder
Date : 2025-08-12 Size : 260kb User : 一天 -
FSK modulation and demodulation process, and VHDL simulation
Date : 2025-08-12 Size : 51kb User : 一天 -
This is a Huffman decoder with dynamic Huffcode tables. A Testbench for a jpg file is include.
Date : 2025-08-12 Size : 194kb User : PCB -
Sport vhdl interface for DSP
Date : 2025-08-12 Size : 111kb User : stefano -
It is a implementation of FSK, ASK, modulation.
Date : 2025-08-12 Size : 9kb User : elpable -
what is the output of this small program? ans- this will loop indefinitely. value of i in main() will never exceeds 1.
Date : 2025-08-12 Size : 51kb User : jai prakash -
8b1ob
Date : 2025-08-12 Size : 3kb User : gg