VHDL-FPGA-Verilog List Page 3262

VHDL-FPGA-Verilog list

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timer Downloaded：0: Based on the VHDL language, to achieve the clock function, display time from 00:00:00 to 23:59:59, and the output signal is converted to digital control signals
Update : 2025-04-19 Size : 487kb Publisher : 陈伟
fft Downloaded：0: this code evaluate FFT for 32 point
Update : 2025-04-19 Size : 115kb Publisher : ali
IQDemod Downloaded：0: the I_Q Demoder is usefull for communication process in FPGA
Update : 2025-04-19 Size : 1kb Publisher : ali
multiplier Downloaded：0: this is a multiplier in VHDL
Update : 2025-04-19 Size : 1kb Publisher : ali
CyclonePLL Downloaded：0: Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle a
Update : 2025-04-19 Size : 541kb Publisher : 裴雷
61EDA_D888 Downloaded：0: Based on Verilog HDL Taxi Accounting System
Update : 2025-04-19 Size : 416kb Publisher : panda chen
DES-HDL Downloaded：0: HDL implementation of the DES with the encryption algorithm, by pre-simulation, we want to help
Update : 2025-04-19 Size : 27kb Publisher : su
Cymometer Downloaded：0: Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
Update : 2025-04-19 Size : 572kb Publisher : 石头
VHDL Downloaded：0: VHDL language design with seven-segment display decoder
Update : 2025-04-19 Size : 1kb Publisher : 冷与
lock Downloaded：0: Design an 8-bit serial digital code lock control circuit
Update : 2025-04-19 Size : 1kb Publisher : 冷与
vhdl Downloaded：0: Responder a vhdl design
Update : 2025-04-19 Size : 1kb Publisher : 冷与
DSP_FIR_Lab Downloaded：0: This is DSP FIR lab, it includes there forms to implement FIR, direct form, transposed form and time mulitple form, all code has been tested on Modesim.
Update : 2025-04-19 Size : 7kb Publisher : hongwan

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