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VHDL-FPGA-Verilog list
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Using Cyclone EP1C3, VHDL program algorithm of the signal waveform of real-time sampling and playback at the same time capable of measuring the frequency of the signal in time domain, through a MCU 8-bit parallel interfa
Update : 2025-04-04 Size : 4.53mb Publisher : 姚益武

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code-decoder
Update : 2025-04-04 Size : 1kb Publisher : 科林

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Stepper motor rotation control program can be used for variable speed, and mixed use encoder
Update : 2025-04-04 Size : 1kb Publisher : 强强

802.3an ldpc decoder verilog 源码
Update : 2025-04-04 Size : 864kb Publisher : 杨振飞

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this is a verilog source code which can count the greatest common divider .
Update : 2025-04-04 Size : 305kb Publisher : 杨振飞

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30 miao ji shi
Update : 2025-04-04 Size : 1kb Publisher : 蓝子

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xmncdjdkddd dsef
Update : 2025-04-04 Size : 156kb Publisher : 蓝子

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4 bit parallel add-sub with test bench.. in vhdl..
Update : 2025-04-04 Size : 1kb Publisher : harkirat

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4:1 multiplexer using with select.. Test Bench included..
Update : 2025-04-04 Size : 1kb Publisher : harkirat

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8:1 priority encoder.. Test Bench included..
Update : 2025-04-04 Size : 1kb Publisher : harkirat

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async counter,, test bench included..
Update : 2025-04-04 Size : 1kb Publisher : harkirat

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asynchronous D-FlipFlop & JK-FlipFlop.. with test bench.
Update : 2025-04-04 Size : 2kb Publisher : harkirat
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