VHDL-FPGA-Verilog List Page 3334

VHDL-FPGA-Verilog list

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CustomInstruction Downloaded：0: CustomInstruction embedded in the FPGA core sopc user instructions on the preparation of
Update : 2025-03-19 Size : 109kb Publisher : 成吉
timeinterrupt Downloaded：0: timeinterrupt in the FPGA to achieve timing, counting interrupt function
Update : 2025-03-19 Size : 3kb Publisher : 成吉
frq_cnt Downloaded：0: Frequency Counter in VHDL.
Update : 2025-03-19 Size : 3kb Publisher : mr_adam
freqcntr2 Downloaded：0: Frequency counter 2 in VHDL
Update : 2025-03-19 Size : 7kb Publisher : mr_adam
uart_latest.tar Downloaded：0: Universal Asynchronous RT in VHDL.
Update : 2025-03-19 Size : 9kb Publisher : mr_adam
i2c_wb_wrapper_latest.tar Downloaded：0: I2C+Wishbone in VHDL
Update : 2025-03-19 Size : 13kb Publisher : mr_adam
prob2 Downloaded：0: SSTL
Update : 2025-03-19 Size : 1kb Publisher : gao
prob1 Downloaded：0: UART
Update : 2025-03-19 Size : 1kb Publisher : gao
pll Downloaded：0: Be able to run a phase-locked loop procedure is very good, can be used in many ways
Update : 2025-03-19 Size : 1kb Publisher : 李俊
vhdl Downloaded：0: Experiment content, in order to validate memory memory works, need to use test case
Update : 2025-03-19 Size : 1kb Publisher : 李明
oc_i2c_master Downloaded：0: I 2 C is a 2-line bidirectional serial interface, very suitable for chip-level communication. Because SOPC Builder does not provide I 2 C core, as described in this section I 2 C core is produced by Richard Herveille and
Update : 2025-03-19 Size : 254kb Publisher : xuai
JPEG Downloaded：0: This paper describes the static image compression (JPEG) coding algorithm is the basic principle of compression process of the implementation process and its important discrete cosine transform (DCT) Algorithm theory and
Update : 2025-03-19 Size : 41kb Publisher : xuai

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