VHDL-FPGA-Verilog List Page 3382

VHDL-FPGA-Verilog list

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T_uart Downloaded：0: CPLD implementation of the code to send the module to design key detection module, and key by constructing the UART to send the module to send to the serial port debugging tool in the view.- Send format: one start bit+8
Update : 2025-03-18 Size : 1kb Publisher : 虎
interface Downloaded：0: MCU and CPLD' s interface can read and write data.
Update : 2025-03-18 Size : 1kb Publisher : 虎
ddfs Downloaded：0: Direct digital frequency synthesizer, the entire project file are in the simulation is also directly be able to use.
Update : 2025-03-18 Size : 467kb Publisher : 虎
crc Downloaded：0: Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
Update : 2025-03-18 Size : 426kb Publisher : 虎
rstk-0.7.tar Downloaded：0: archivo reed solom para utilizar en decodificacion de television digital esta en vhdl
Update : 2025-03-18 Size : 174kb Publisher : Gus
I2C_xo Downloaded：0: IIC' s verilog source code, you can Lattice' s XO DEMO board to run IIC code. Included documentation
Update : 2025-03-18 Size : 6.26mb Publisher : 高小高
Digita_mediante_VHDL Downloaded：0: practica de ejercicios de vhdl
Update : 2025-03-18 Size : 186kb Publisher : Gus
Chuongtrinh_mau Downloaded：0: vhdl codes examples
Update : 2025-03-18 Size : 3.94mb Publisher : chicken09
8-led-VHDL Downloaded：0: 8 water lamps program design, which is a VHDL program
Update : 2025-03-18 Size : 107kb Publisher : luo
Divider-design-in-three-ways Downloaded：0: Divider design in three ways (often used to produce second pulse)
Update : 2025-03-18 Size : 2kb Publisher : luo
ocidec1 Downloaded：0: The hard disk controller
Update : 2025-03-18 Size : 37kb Publisher : liwei
FPGA_Development_of_full-Gong_Lue Downloaded：0: FPGA_Development_of_full-Gong_Lue
Update : 2025-03-18 Size : 10.57mb Publisher : liu

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