EP2C35 official development board schematics, is altera of official information. Fpga circuit design is a good reference model. Update : 2025-03-18
Size : 343kb
Publisher : ami
Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, onc Update : 2025-03-18
Size : 2.1mb
Publisher : 力文
Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit freque Update : 2025-03-18
Size : 632kb
Publisher : 力文
Written by Verlog HDL ,a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display. Update : 2025-03-18
Size : 1008kb
Publisher : 吴海燕