VHDL-FPGA-Verilog List Page 3564

VHDL-FPGA-Verilog list

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EDA_tel_counter Downloaded：0: EDA teaching in the chamber to achieve telephone billing function
Update : 2025-03-10 Size : 52kb Publisher : lian
cronometro Downloaded：0: This is the program of a timer with a accuracy of ms
Update : 2025-03-10 Size : 1.47mb Publisher : Sergio
filtru_fi Downloaded：0: This is a filter fir implemeted in vhdl, i hope it will work :)
Update : 2025-03-10 Size : 1kb Publisher : om
uart Downloaded：0: This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.
Update : 2025-03-10 Size : 1kb Publisher : Balazs Jozsa
cam Downloaded：0: This Verilog desription shows an example for a Content Adressable Memory (CAM)
Update : 2025-03-10 Size : 1kb Publisher : balloo
syn_fifo Downloaded：0: A Verilog description of a synchronous FIFO memory circuit
Update : 2025-03-10 Size : 1kb Publisher : balloo
aFifo Downloaded：0: This is an implementation of an Asynchronous FIFO written in Verilog 2001.
Update : 2025-03-10 Size : 2kb Publisher : balloo
divide_by_3 Downloaded：0: This module divides the input clock frequency by 3.
Update : 2025-03-10 Size : 1kb Publisher : balloo
I2C_receiver Downloaded：0: To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
Update : 2025-03-10 Size : 2kb Publisher : lj
asynchronoussignal Downloaded：0: Description of cross-clock domain analysis, analyze and solve design problems in asynchronous clock synchronization.
Update : 2025-03-10 Size : 467kb Publisher : 张然峰
cymometer Downloaded：0: Digital frequency meter measuring frequency of the source code to achieve the maximum 30MHz
Update : 2025-03-10 Size : 169kb Publisher : 王继超
gh_vhdl_lib_3_47 Downloaded：0: The VHDL component library Opencores version 3.47
Update : 2025-03-10 Size : 752kb Publisher : 贺明辉

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