VHDL-FPGA-Verilog List Page 3584

VHDL-FPGA-Verilog list

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cpld_config Downloaded：0: spartan3e starter kit,cpld configuration file
Update : 2025-03-07 Size : 1kb Publisher : xm
QUARTUSIIIntroduce Downloaded：0: This manual is aimed at readers of the Quartus II software for beginners, it provides an overview of programmable logic in the Quartus II design software
Update : 2025-03-07 Size : 2.95mb Publisher : 光辉
adc_dac_normalizador_v_2 Downloaded：0: This is an examples for converting decimal number to binary
Update : 2025-03-07 Size : 2.18mb Publisher : erix
FIR_Direkt_ak Downloaded：0: VHDL code of the direct-type 22-order FIR filter. Fa = 48 kHz, Fc = 10kHz can be under the ModelSim simulation, FPGA realization.
Update : 2025-03-07 Size : 1kb Publisher : 李乔
FIR_Direkt_BAB_P Downloaded：0: Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
Update : 2025-03-07 Size : 1kb Publisher : 李乔
Spartan-3_NeuralNetwork_3-layer_feedforward_backp Downloaded：0: The aim of this project is the design and implementation of a system simulating a NN in the Spartan-3 Starter Board of Xilinx. The NN will be a 3-layer feedforward backpropagation.
Update : 2025-03-07 Size : 1.41mb Publisher : duzos
AD9826 Downloaded：0: ad9826
Update : 2025-03-07 Size : 129kb Publisher : lin
xilinx_ref_guide Downloaded：0: Xilinx Blockset Reference Guide
Update : 2025-03-07 Size : 997kb Publisher : hidon
fenpinqi Downloaded：0: Dual frequency many times: even several times frequency should be more familiar with all the sub-frequency, through the counter count is entirely achievable. Such as N times the frequency of even-numbered points, then by
Update : 2025-03-07 Size : 1kb Publisher : 范尼
Verilog Downloaded：0: This is a comparison of VERILOG HDL source code commonly used devices, including registers, shifter, etc.
Update : 2025-03-07 Size : 111kb Publisher : 张军政
rafal2 Downloaded：0: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Update : 2025-03-07 Size : 919kb Publisher : nukom
fft_verilog Downloaded：0: FFT IP core
Update : 2025-03-07 Size : 7kb Publisher : chris

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