VHDL-FPGA-Verilog List Page 3592

VHDL-FPGA-Verilog list

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BCD Downloaded：0: BCD digital display in the DE2 platform quartus
Update : 2025-03-07 Size : 56kb Publisher : johnson
lift Downloaded：0: (1) the realization of four-storey elevator with VHDL controller operation. (2) elevator button with a lock to run in place of (unlock power), low run, can not run high. (3) on each floor with elevator at the entrance to
Update : 2025-03-07 Size : 283kb Publisher : 管皮皮
lonely Downloaded：0: 1 code table
Update : 2025-03-07 Size : 566kb Publisher : 吳員外
mc8051 Downloaded：0: source code of the implement of 8051,by the source code ,we can learn the implement principle of 8051 CPU
Update : 2025-03-07 Size : 197kb Publisher : xu_xf
counter Downloaded：0: the difference counter ,it can help to learn VHDL ,it can also be as a modular in your project
Update : 2025-03-07 Size : 1kb Publisher : xu_xf
pwm Downloaded：0: verilog to achieve PWM development environment QUARTUS II7.0
Update : 2025-03-07 Size : 53kb Publisher : exun
usb_vhdl Downloaded：0: a reference implement of the control interface of USB device
Update : 2025-03-07 Size : 59kb Publisher : xu_xf
rs_enc Downloaded：0: This is a VHDL prepared with RS channel coding procedures
Update : 2025-03-07 Size : 1kb Publisher : chenxiaoming
tcm_enc Downloaded：0: This is a VERILOG HDL prepared with TCM channel coding
Update : 2025-03-07 Size : 1kb Publisher : chenxiaoming
interleaver Downloaded：0: This is a prepared using VHDL interleaver, the use of interleaver enables interference by the sudden randomized into
Update : 2025-03-07 Size : 1kb Publisher : chenxiaoming
conv_enc Downloaded：0: This is a VERILOG HDL with the preparation of procedures for the convolutional codes
Update : 2025-03-07 Size : 1kb Publisher : chenxiaoming
viterbi Downloaded：0: This is a language VERILOG HDL by the viterbi decoding process
Update : 2025-03-07 Size : 2kb Publisher : chenxiaoming

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