VHDL-FPGA-Verilog List Page 3709

VHDL-FPGA-Verilog list

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yuv_rgb Downloaded：0: Complete video streaming ITUR656 standard data format to RGB conversion. Test module
Update : 2025-01-24 Size : 2kb Publisher : 黄涛
sel_stamp Downloaded：0: Money function can be realized stamp vending machine, to buy two stamps, one dollar and the Pentagon
Update : 2025-01-24 Size : 1kb Publisher : 黄涛
fadder Downloaded：0: The use of two and a half adder to form the full adder is a simple entry-vhdl language
Update : 2025-01-24 Size : 1kb Publisher : rosebud
VGA_Ctrl Downloaded：0: Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to write a response to Avalon from the CPU ports of the control sig
Update : 2025-01-24 Size : 1kb Publisher : 黄涛
key Downloaded：0: KEY SCAN VHDL
Update : 2025-01-24 Size : 148kb Publisher : weibao
I2C_Controller Downloaded：0: Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656
Update : 2025-01-24 Size : 1kb Publisher : 黄涛
ADCINT Downloaded：0: ADC0809
Update : 2025-01-24 Size : 82kb Publisher : weibao
ROM16_8 Downloaded：0: ROM 16*8
Update : 2025-01-24 Size : 90kb Publisher : weibao
digi_clock Downloaded：0: VERILOG prepared with digital electronic clock with a nixie tube display time
Update : 2025-01-24 Size : 3kb Publisher : 黄涛
dds_gen Downloaded：0: FPGA-based phase adjustable frequency DDS signal generator
Update : 2025-01-24 Size : 5kb Publisher : liulifeng
Simulate Downloaded：0: FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.
Update : 2025-01-24 Size : 1kb Publisher : Hongjun
chuanbingzhuanhuan Downloaded：0: And the string conversion of the code is relying on the synchronization state machine to achieve its control. In fact, string conversion circuit in the actual use of, or more, particularly in the area of communication li
Update : 2025-01-24 Size : 1kb Publisher : 盛忠良

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