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VHDL-FPGA-Verilog list
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CT2 IDCT2 transform C code. After successful testing for altera, bear fruit.
Update : 2025-01-21 Size : 1.12mb Publisher : 金夕

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Improved Iterative CORDIC algorithm cos structure, applicable to altera.
Update : 2025-01-21 Size : 8kb Publisher : 金夕

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Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
Update : 2025-01-21 Size : 3kb Publisher : 金夕

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Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Update : 2025-01-21 Size : 3kb Publisher : 张堃

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cpu VHDL Design and Implementation of multiplication addition subtraction
Update : 2025-01-21 Size : 1.92mb Publisher : 郭红

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poc of VHDL handshake signal to achieve the detailed design of interactive
Update : 2025-01-21 Size : 114kb Publisher : 郭红

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Atan is the codic algorithm virilog procedures, module is structured as follows: Core Structure: sc_corproc.vhd-> p2r_cordic.vhd-> p2r_cordicpipe.vhd
Update : 2025-01-21 Size : 3kb Publisher : 张堃

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VHDL-based preparation and implementation of the POC to achieve three-way handshake
Update : 2025-01-21 Size : 293kb Publisher : 郭红

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Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.
Update : 2025-01-21 Size : 3kb Publisher : 张堃

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Sin is codic floating-point algorithm C procedures, including fixed-point and floating-point procedures, has been validated.
Update : 2025-01-21 Size : 5kb Publisher : 张堃

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err
Update : 2025-01-21 Size : 10kb Publisher : 张堃

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8b10b reference design
Update : 2025-01-21 Size : 74kb Publisher : 凌峰
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