VHDL-FPGA-Verilog List Page 394

VHDL-FPGA-Verilog list

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vga256 Downloaded：0: FPGA VGA
Update : 2025-01-18 Size : 291kb Publisher : 解剑絮
led_water Downloaded：0: FPGA led_water
Update : 2025-01-18 Size : 178kb Publisher : 解剑絮
LED_bak Downloaded：0: LED light water, has been in xilinx development board test is feasible.
Update : 2025-01-18 Size : 2kb Publisher : 郝锐敏
PWM_Gen_150kHz Downloaded：0: 150KHz PWM Generator with single pulse generation which can be enabled or disabled. Can be used for debug purposes where the required number of PWM pulses can be generated
Update : 2025-01-18 Size : 2kb Publisher : Alex
AD652 Downloaded：0: Clock generator for AD652-AEC. Generates switchbale 2,174MHz Clock
Update : 2025-01-18 Size : 1kb Publisher : Alex
rms_mean_measure Downloaded：0: Measurement of RMS and Mean value
Update : 2025-01-18 Size : 2kb Publisher : Alex
sine_pwm_gen Downloaded：0: Sine PWM Generator for a sine frequency of 0..255Hz. Signal to a two phase mode is available
Update : 2025-01-18 Size : 5kb Publisher : Alex
ADC-ADS7230 Downloaded：0: ADC ADS7230 - ADC module in VHDL for ADS 7230 (Texas Instruments)
Update : 2025-01-18 Size : 2kb Publisher : Alex
1 Downloaded：0: Use 89C51 microcontroller production of simple signal generator, can achieve four waveforms. Sine, sawtooth, square, triangle wave. Signal frequency 1HZ-10KHZ
Update : 2025-01-18 Size : 4kb Publisher : 吴晓宸
yi Downloaded：0: shifting register
Update : 2025-01-18 Size : 4.2mb Publisher : lily
99multiply Downloaded：0: 99 multiplication table, write by VHDL, simulation and DE2 board have been tested to run successfully
Update : 2025-01-18 Size : 1.19mb Publisher : yang
NoSocAdau1761_zyz Downloaded：0: 在Zedboard上测试Adau1761录放音郑郁正 1. 这个项目来自网上：Zedboard_d base_project。 2. 项目不是vivado工程，而是ise工程。 3. 项目的功能是将PC机播放的声音从Zedboard的Line In声音口输入，从耳机口输出。 4. 不支持话筒输入，也就是Micphone不起作用。 5. 不支持LineOut喇叭口输出。 6. 输出音量可以通过sw0、sw1选择，组合支持四级音量。测试
Update : 2025-01-18 Size : 1.15mb Publisher : 郑郁正

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