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VHDL-FPGA-Verilog list
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FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even on the serial port, the data will have to go under, 9600 baud, one stop bit, SDRAM clock is 96MHz, automatically gen
Update : 2025-01-18 Size : 5.33mb Publisher : Grace

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FPGA-based serial transceiver procedures, 115200 baud rate, pro-test, can be used.
Update : 2025-01-18 Size : 2.27mb Publisher : Grace

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Four one of the selector FPGA source code, including the module Verilog files and test testbench files
Update : 2025-01-18 Size : 112kb Publisher : JJ

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8 full adder, including half adder, full adder Verilog file, Verilog file, 8 full adder Verilog files, and 8 full adder test testbench file
Update : 2025-01-18 Size : 138kb Publisher : JJ

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16-bit binary counter and design codes and test code (vhdl)
Update : 2025-01-18 Size : 2kb Publisher : cassy

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Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
Update : 2025-01-18 Size : 15kb Publisher : DY

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Implemented in FPGA car tracking control, and the use of infrared remote control car
Update : 2025-01-18 Size : 3.76mb Publisher : wang

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Pong game use VGA controller
Update : 2025-01-18 Size : 17kb Publisher : Sergiu

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Achieve RGB TTL signal output- can push any resolution TFT
Update : 2025-01-18 Size : 54kb Publisher : 黄同意

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Digital filter in VHDL
Update : 2025-01-18 Size : 1kb Publisher : jossss

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Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter shaping filter with FIR, finally get the outp
Update : 2025-01-18 Size : 6.47mb Publisher : 猪头

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FPGA source code is the use of EP4CE15F17C8N hardware platform for water lamp source
Update : 2025-01-18 Size : 3.1mb Publisher :
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