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VHDL-FPGA-Verilog list
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bch encoder+ decoder source code, Flash controller, communications are needed Oh
Update : 2025-01-11 Size : 133kb Publisher : linchan

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In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
Update : 2025-01-11 Size : 463kb Publisher : lovenevol

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verilog hdl coding DDR sdram control for fpga
Update : 2025-01-11 Size : 27kb Publisher : 王郁

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NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful
Update : 2025-01-11 Size : 254kb Publisher : weikang

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Six floors of elevator control systems The VHDL description also includes the system simulation graphics
Update : 2025-01-11 Size : 159kb Publisher : key

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Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware description language of the people to see!
Update : 2025-01-11 Size : 52kb Publisher : 小方

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High-speed FIFO, verilog design. Speed up to 130MHz
Update : 2025-01-11 Size : 105kb Publisher :

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Examples of Verilog language, the novice has to learn very helpful examples of
Update : 2025-01-11 Size : 111kb Publisher : 心音

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description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of
Update : 2025-01-11 Size : 35kb Publisher : digua

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Using FPGA to communicate with PC through RS232,
Update : 2025-01-11 Size : 3kb Publisher : 苏山河

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Programmable logic device CPLD and MCU for two-way communication of the source
Update : 2025-01-11 Size : 1kb Publisher : jjaai

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This procedure is a VHDL language electronic code lock function, the entire system is divided into three modules, one for the control module, two for the keyboard display module, three modules for the treatment
Update : 2025-01-11 Size : 263kb Publisher : 敬礼
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