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VHDL-FPGA-Verilog list
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the lattice-CAS documentation, the development of cpld be friends with
Date : 2025-08-12 Size : 645kb User : evan -
ispLEVER CPLD, FPGA development environment succession
Date : 2025-08-12 Size : 1023kb User : evan -
SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparatio
Date : 2025-08-12 Size : 3kb User : 林博 -
VHDL good for serial communication. Three die fast, occurred clock, sending and receiving process
Date : 2025-08-12 Size : 122kb User : 刘三 -
some others used the VHDL source code, and I hope to you and useful!
Date : 2025-08-12 Size : 165kb User : 大大头 -
des vhld source procedures completed DES encoding and decoding
Date : 2025-08-12 Size : 5kb User : 王亮 -
achieve fft
Date : 2025-08-12 Size : 61kb User : processor -
-- PCI Target Interface Design for XC73144---- Synopsys VHDL Solution using Xilinx XC7000 Library
Date : 2025-08-12 Size : 3kb User : processor -
with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Date : 2025-08-12 Size : 10kb User : 单明 -
server board controller is contained in the AHDL procedures, including schematic compiler, the use EPM7128 (CPLD).
Date : 2025-08-12 Size : 514kb User : 老罗 -
stepper motor control, controllers, motor control VHDL source
Date : 2025-08-12 Size : 1kb User : 刘 -
Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Date : 2025-08-12 Size : 2kb User : 谢树扬