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VHDL-FPGA-Verilog list
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Update : 2024-12-26 Size : 40.54mb Publisher : miemiemie

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CRC32:polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) * data width: 8 CRC16:polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) * data width: 8
Update : 2024-12-26 Size : 2kb Publisher : FYSG

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EEPROM project, the realization of the basic reading and writing for reference. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify pin configuration and logic control according to its own
Update : 2024-12-26 Size : 156kb Publisher : shaoyang_v

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FPGA language is used to realize the network transmission of TCP/IP protocol based on W5300 chip. The W5300 part of the program realizes IP packaging, and only the input and output pins and the clock, reset and so on.
Update : 2024-12-26 Size : 23.44mb Publisher : 董教授

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RS232 transmission based on FPGA,
Update : 2024-12-26 Size : 34.51mb Publisher : 董教授

With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core
Update : 2024-12-26 Size : 18.41mb Publisher : 董教授

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The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configuration according to its own hardware.
Update : 2024-12-26 Size : 125kb Publisher : shaoyang_v

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An electronic clock that can be used for 24 hours, using the TEC-8 test platform
Update : 2024-12-26 Size : 1.14mb Publisher : 科比的

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The memory control code of spi interface is very simple and practical for reference.
Update : 2024-12-26 Size : 288kb Publisher : 一粒尘埃

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An ECC error correction algorithm based on hamming code can be used for reference
Update : 2024-12-26 Size : 1kb Publisher : 一粒尘埃

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Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.
Update : 2024-12-26 Size : 24kb Publisher : 一粒尘埃

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Qspi interface control, including spi, dual spi, quad spi, for reference.
Update : 2024-12-26 Size : 3kb Publisher : 一粒尘埃
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