This is my ISP programming experiment in the preparation of an independent description of the use of behavior to achieve the prescaler, through two parallel processes on the input signal CLK to 8 minutes frequency, duty cycle 1:7

fen1to7
.......\clk_div.acf
.......\clk_div.fit
.......\clk_div.hex
.......\clk_div.hif
.......\clk_div.mmf
.......\clk_div.ndb
.......\clk_div.pin
.......\clk_div.pof
.......\clk_div.rpt
.......\clk_div.scf
.......\clk_div.snf
.......\clk_div.sof
.......\CLK_DIV.sym
.......\clk_div.ttf
.......\clk_div.vhd
.......\LIB.DLS
.......\U0392087.DLS
.......\U1794970.DLS
.......\U8629063.DLS

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