Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder location for the ECC error procedures.

ECCErrLoc
.........\ECCErrLoc.ise
.........\ECCErrLoc.ise_ISE_Backup
.........\ECCErrLoc.restore
.........\ECCErrLoc.vhd
.........\ECCErrLoc_summary.html
.........\_xmsgs
eccGen256byte
.............\AutoConstraint_eccGen256byte.sdc
.............\dist_mem_gen_ds322.pdf
.............\dist_mem_gen_release_notes.txt
.............\ecc.coe
.............\ecc.coe.bak
.............\eccGen256byte.cel
.............\eccgen256byte.cmd_log
.............\eccGen256byte.fse
.............\eccGen256byte.htm
.............\eccGen256byte.ise
.............\eccGen256byte.ise_ISE_Backup
.............\eccGen256byte.log
.............\eccGen256byte.map
.............\eccGen256byte.ntrc_log
.............\eccGen256byte.restore
.............\eccGen256byte.sap
.............\eccGen256byte.sdc
.............\eccGen256byte.tap
.............\eccGen256byte.ucf
.............\eccGen256byte.vhd
.............\eccGen256byte.vhd.bak
.............\eccGen256byte_guide.ncd
.............\eccGen256byte_map.map
.............\eccGen256byte_summary.html
.............\eccgen256byte_summary.xml
.............\eccTab256.asy
.............\eccTab256.mif
.............\eccTab256.ngc
.............\eccTab256.sym
.............\eccTab256.v
.............\eccTab256.veo
.............\eccTab256.vhd
.............\eccTab256.vho
.............\eccTab256.xco
.............\eccTab256_dist_mem_gen_v3_3_xst_1_xsd
.............\.....................................\dist_mem_gen_v3_3
.............\.....................................\.................\sub00
.............\.....................................\dump.xst
.............\.....................................\........\eccTab256_dist_mem_gen_v3_3_xst_1.prj
.............\.....................................\........\.....................................\ngx
.............\.....................................\........\.....................................\...\notopt
.............\.....................................\........\.....................................\...\opt
.............\eccTab256_flist.txt
.............\eccTab256_summary.html
.............\eccTab256_xmdf.tcl
.............\FIFO8x16.asy
.............\FIFO8x16.ngc
.............\FIFO8x16.sym
.............\FIFO8x16.v
.............\FIFO8x16.veo
.............\FIFO8x16.vhd
.............\FIFO8x16.vho
.............\FIFO8x16.xco
.............\FIFO8x16_fifo_generator_v3_3_xst_1.lso
.............\FIFO8x16_fifo_generator_v3_3_xst_1_vhdl.prj
.............\FIFO8x16_flist.txt
.............\FIFO8x16_readme.txt
.............\FIFO8x16_xmdf.tcl
.............\fifo_generator_release_notes.txt
.............\fifo_generator_ug175.pdf
.............\layer0.sro
.............\layer0.tlg
.............\rpt_eccGen256byte_areasrr.htm
.............\src_core
.............\........\eccTab256.mif
.............\........\eccTab256.ngc
.............\........\eccTab256.sym
.............\........\eccTab256.v
.............\........\eccTab256.veo
.............\........\eccTab256.vhd
.............\........\eccTab256.vho
.............\........\eccTab256.xco
.............\tb_ecc.vhd
.............\tb_ecc_vhd.fdo
.............\tb_ecc_vhd.udo
.............\templates
.............\.........\coregen.xml
.............\timing.twr
.............\tmp
.............\...\_cg
.............\transcript
.............\verif
.............\.....\eccGen256byte.vif
.............\.....\eccGen256byte_bb.v
.............\vsim.wlf
.............\wave.do
.............\work
.............\....\eccgen256byte
.............\....\.............\behavioral.asm
.............\....\.............\behavioral.dat
.............\....\.............\_primary.dat
.............\....\ecctab256

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