USB v1.1 RTL and design specification

doc
...\c8051.pdf
...\c8051_a.pdf
...\c8051_b.pdf
...\c8051_dsn.pdf
...\c8051_spec.pdf
...\c8051_spec_ok.pdf
src_verilog
...........\core
...........\....\ALU_R.v
...........\....\C8051_S.v
...........\....\CLOCK_CONTROL_R.v
...........\....\CONTROL_UNIT_R.v
...........\....\ISR_R.v
...........\....\MEMORY_CONTROL_R.v
...........\....\OCI_R.v
...........\....\PORTS_R.v
...........\....\RAM_SFR_CONTROL_R.v
...........\....\SERIAL_R.v
...........\....\TIMER_0_1_R.v
...........\....\UTILITY.v
...........\tb
...........\..\chip
...........\..\....\chip8051.v
...........\..\....\chipoci.v
...........\..\....\chippad.v
...........\..\....\chipram.v
...........\..\....\chiprom.v
...........\..\....\chipsfr.v
...........\..\....\utility.v
...........\..\tb.v
tests
.....\default
.....\.......\acscomp.txt
.....\.......\acsdiff.txt
.....\.......\extrom.hex
.....\.......\introm.hex
.....\.......\simcomp.txt
.....\.......\simdiff.txt
.....\.......\stim.txt
.....\.......\test.asm
.....\.......\time.txt

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