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buf_tree_pol.tar
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Construct buffered routing tree for VLSI interconnects in a Manhanttan layout plane for a given set of terminals, guarantee polarity of the terminals agree with each other
Update : 2025-03-11 Size : 33kb Publisher : Ernesto Liu
Minaret.tar
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Minaret: retiming edge-triggered circuit for improved performance and higher clock frequency by moving combinational logic gates across sequential elements
Update : 2025-03-11 Size : 2.69mb Publisher : Ernesto Liu
FengShui.tar
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FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea of gate and standard cell designs, scales well into million gate designs
Update : 2025-03-11 Size : 571kb Publisher : Ernesto Liu
66666
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product-sale-manage system. it includes product sale
Update : 2025-03-11 Size : 2.51mb Publisher : dfd
GraduationProjectGuidelines
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This is the guiding thesis of the book, hoping to have a certain number of new help. 搜索
Update : 2025-03-11 Size : 185kb Publisher : 黄冠兵
student
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School management system. Although挺多online, but this definitely can. And it just works.
Update : 2025-03-11 Size : 241kb Publisher : fang
010_BUS.RAR
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IEE10 for power system analysis of a typical node architecture
Update : 2025-03-11 Size : 13kb Publisher : liu
043_BUS.RAR
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IEE43 for power system analysis of a typical node architecture
Update : 2025-03-11 Size : 33kb Publisher : liu
039_BUS.RAR
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Power System Analysis for the IEEE39 system structure of a typical node
Update : 2025-03-11 Size : 210kb Publisher : liu
030_BUS.RAR
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Power System Analysis for the IEEE30 system structure of a typical node
Update : 2025-03-11 Size : 178kb Publisher : liu
057_BUS.RAR
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Power System Analysis for the IEEE57 system structure of a typical node
Update : 2025-03-11 Size : 312kb Publisher : liu
118_BUS.RAR
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Power System Analysis for the IEEE118 system structure of a typical node
Update : 2025-03-11 Size : 669kb Publisher : liu
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