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RSOriginal

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  • Update : 2012-11-26
  • Size : 11.22mb
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  • Author :陈****
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Introduction - If you have any usage issues, please Google them yourself
Reed-Solomon channel coding are widely used in DVB
Packet file list
(Preview for download)
RS
..\code version1
..\.............\Document
..\.............\........\KESBLOCK文档说明.doc
..\.............\........\RS Decoder架构.doc
..\.............\........\time-wave
..\.............\........\.........\AndyTiming.exe
..\.............\........\.........\control1.atd
..\.............\........\.........\cseeoutput.atd
..\.............\........\.........\fifo_out.atd
..\.............\........\.........\input.atd
..\.............\........\.........\input.bmp
..\.............\........\.........\kes.atd
..\.............\........\.........\output.atd
..\.............\ModelSim_SE
..\.............\...........\Csee_tb
..\.............\...........\.......\testcsee.v
..\.............\...........\Fifo_tb
..\.............\...........\.......\fifo16.v
..\.............\...........\.......\fifo16.v.bak
..\.............\...........\.......\fifo204.v
..\.............\...........\.......\fifotestbench.cr.mti
..\.............\...........\.......\fifotestbench.mpf
..\.............\...........\.......\FIFO_GENERATOR_V2_0.v
..\.............\...........\.......\fifo_tb.v
..\.............\...........\.......\fifo_tb.v.bak
..\.............\...........\.......\vsim.wlf
..\.............\...........\.......\wave.do
..\.............\...........\.......\work
..\.............\...........\.......\....\@f@i@f@o_@g@e@n@e@r@a@t@o@r_@v2_0
..\.............\...........\.......\....\.................................\verilog.asm
..\.............\...........\.......\....\.................................\_primary.dat
..\.............\...........\.......\....\.................................\_primary.vhd
..\.............\...........\.......\....\fifo16
..\.............\...........\.......\....\......\verilog.asm
..\.............\...........\.......\....\......\_primary.dat
..\.............\...........\.......\....\......\_primary.vhd
..\.............\...........\.......\....\fifo204
..\.............\...........\.......\....\.......\verilog.asm
..\.............\...........\.......\....\.......\_primary.dat
..\.............\...........\.......\....\.......\_primary.vhd
..\.............\...........\.......\....\fifotb
..\.............\...........\.......\....\......\verilog.asm
..\.............\...........\.......\....\......\_primary.dat
..\.............\...........\.......\....\......\_primary.vhd
..\.............\...........\.......\....\fifo_generator_v2_0_bhv_ver_as
..\.............\...........\.......\....\..............................\verilog.asm
..\.............\...........\.......\....\..............................\_primary.dat
..\.............\...........\.......\....\..............................\_primary.vhd
..\.............\...........\.......\....\fifo_generator_v2_0_bhv_ver_fifo16
..\.............\...........\.......\....\..................................\verilog.asm
..\.............\...........\.......\....\..................................\_primary.dat
..\.............\...........\.......\....\..................................\_primary.vhd
..\.............\...........\.......\....\fifo_generator_v2_0_bhv_ver_ss
..\.............\...........\.......\....\..............................\verilog.asm
..\.............\...........\.......\....\..............................\_primary.dat
..\.............\...........\.......\....\..............................\_primary.vhd
..\.............\...........\.......\....\fifo_register
..\.............\...........\.......\....\.............\verilog.asm
..\.............\...........\.......\....\.............\_primary.dat
..\.............\...........\.......\....\.............\_primary.vhd
..\.............\...........\.......\....\gfadder
..\.............\...........\.......\....\.......\verilog.asm
..\.............\...........\.......\....\.......\_primary.dat
..\.............\...........\.......\....\.......\_primary.vhd
..\.............\...........\.......\....\register5_wl
..\.............\...........\.......\....\............\verilog.asm
..\.............\...........\.......\....\............\_primary.dat
..\.............\...........\.......\....\............\_primary.vhd
..\.............\...........\.
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