The use of EDA, VHDL hardware language to achieve digital-to-analog conversion

DAC
...\cmp_state.ini
...\DAC.asm.rpt
...\DAC.cdf
...\DAC.done
...\DAC.fit.eqn
...\DAC.fit.rpt
...\DAC.fit.summary
...\DAC.fld
...\DAC.flow.rpt
...\DAC.map.eqn
...\DAC.map.rpt
...\DAC.map.summary
...\DAC.pin
...\DAC.pof
...\DAC.qpf
...\DAC.qsf
...\DAC.qws
...\DAC.sof
...\DAC.tan.rpt
...\DAC.tan.summary
...\DAC.vhd
...\DAC_assignment_defaults.qdf
...\db
...\..\ADC.asm.qmsg
...\..\ADC.cmp.cdb
...\..\ADC.cmp.ddb
...\..\ADC.cmp.hdb
...\..\ADC.cmp.rdb
...\..\ADC.cmp.tdb
...\..\ADC.cmp0.ddb
...\..\ADC.db_info
...\..\ADC.eco.cdb
...\..\ADC.fit.qmsg
...\..\ADC.hier_info
...\..\ADC.hif
...\..\ADC.icc
...\..\ADC.map.cdb
...\..\ADC.map.hdb
...\..\ADC.map.qmsg
...\..\ADC.pre_map.cdb
...\..\ADC.pre_map.hdb
...\..\ADC.psp
...\..\ADC.rtlv.hdb
...\..\ADC.rtlv_sg.cdb
...\..\ADC.rtlv_sg_swap.cdb
...\..\ADC.sgdiff.cdb
...\..\ADC.sgdiff.hdb
...\..\ADC.signalprobe.cdb
...\..\ADC.sld_design_entry.sci
...\..\ADC.sld_design_entry_dsc.sci
...\..\ADC.syn_hier_info
...\..\ADC.tan.qmsg
...\..\cntr_2b7.tdf
...\..\DAC.asm.qmsg
...\..\DAC.cbx.xml
...\..\DAC.cmp.cdb
...\..\DAC.cmp.hdb
...\..\DAC.cmp.rdb
...\..\DAC.cmp.tdb
...\..\DAC.cmp0.ddb
...\..\DAC.db_info
...\..\DAC.eco.cdb
...\..\DAC.fit.qmsg
...\..\DAC.hier_info
...\..\DAC.hif
...\..\DAC.map.cdb
...\..\DAC.map.hdb
...\..\DAC.map.qmsg
...\..\DAC.pre_map.cdb
...\..\DAC.pre_map.hdb
...\..\DAC.psp
...\..\DAC.rtlv.hdb
...\..\DAC.rtlv_sg.cdb
...\..\DAC.rtlv_sg_swap.cdb
...\..\DAC.sgdiff.cdb
...\..\DAC.sgdiff.hdb
...\..\DAC.signalprobe.cdb
...\..\DAC.sld_design_entry.sci
...\..\DAC.sld_design_entry_dsc.sci
...\..\DAC.syn_hier_info
...\..\DAC.tan.qmsg
...\..\DAC_cmp.qrpt
...\sopc_builder_debug_log.txt

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