FPGA realization of UART serial communication, and newcomers on the Road, please advice

uart_regs
.........\core
.........\....\db
.........\....\myfifo_10.v
.........\....\myfifo_10_bb.v

.........\....\myfifo_10_waveforms.html
.........\....\myfifo_8.v
.........\....\myfifo_8_bb.v

.........\....\myfifo_8_waveforms.html
.........\dev
.........\...\chip_editor.acv
.........\...\cmp_state.ini
.........\...\db
.........\...\..\add_sub_1jh.tdf
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.........\...\..\a_dpfifo_ui81.tdf
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.........\...\..\cntr_9d7.tdf
.........\...\..\cntr_tcb.tdf
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.........\...\..\dpram_81k.tdf
.........\...\..\dpram_h2k.tdf
.........\...\..\dpram_pf51.tdf
.........\...\..\prev_cmp_uart_regs.asm.qmsg
.........\...\..\prev_cmp_uart_regs.fit.qmsg
.........\...\..\prev_cmp_uart_regs.map.qmsg
.........\...\..\prev_cmp_uart_regs.qmsg
.........\...\..\prev_cmp_uart_regs.tan.qmsg
.........\...\..\scfifo_eaq.tdf
.........\...\..\scfifo_eb81.tdf
.........\...\..\scfifo_nbq.tdf
.........\...\..\scfifo_nc81.tdf
.........\...\..\uart_regs-sim.vwf
.........\...\..\uart_regs.asm.qmsg
.........\...\..\uart_regs.cbx.xml
.........\...\..\uart_regs.cmp.cdb
.........\...\..\uart_regs.cmp.hdb
.........\...\..\uart_regs.cmp.logdb
.........\...\..\uart_regs.cmp.rdb
.........\...\..\uart_regs.cmp.tdb
.........\...\..\uart_regs.cmp0.ddb
.........\...\..\uart_regs.dbp
.........\...\..\uart_regs.db_info
.........\...\..\uart_regs.eco.cdb
.........\...\..\uart_regs.fit.qmsg
.........\...\..\uart_regs.hier_info
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.........\...\..\uart_regs.map.cdb
.........\...\..\uart_regs.map.hdb
.........\...\..\uart_regs.map.logdb
.........\...\..\uart_regs.map.qmsg
.........\...\..\uart_regs.pre_map.cdb
.........\...\..\uart_regs.pre_map.hdb
.........\...\..\uart_regs.psp
.........\...\..\uart_regs.pss
.........\...\..\uart_regs.rtlv.hdb
.........\...\..\uart_regs.rtlv_sg.cdb
.........\...\..\uart_regs.rtlv_sg_swap.cdb
.........\...\..\uart_regs.sgdiff.cdb
.........\...\..\uart_regs.sgdiff.hdb
.........\...\..\uart_regs.signalprobe.cdb
.........\...\..\uart_regs.sld_design_entry.sci
.........\...\..\uart_regs.sld_design_entry_dsc.sci
.........\...\..\uart_regs.syn_hier_info
.........\...\..\uart_regs.tan.qmsg
.........\...\..\uart_regs_cmp.qrpt
.........\...\..\uart_regs_hier_info
.........\...\..\uart_regs_sim.qrpt
.........\...\..\uart_regs_syn_hier_info
.........\...\prev_cmp_uart_regs.qmsg
.........\...\sim.cfg
.........\...\uart_regs.asm.rpt
.........\...\uart_regs.done
.........\...\uart_regs.dpf
.........\...\uart_regs.fit.eqn
.........\...\uart_regs.fit.rpt
.........\...\uart_regs.fit.smsg
.........\...\uart_regs.fit.summary
.........\...\uart_regs.fld
.........\...\uart_regs.flow.rpt
.........\...\uart_regs.map.eqn
.........\...\uart_regs.map.rpt
.........\...\uart_regs.map.smsg
.........\...\uart_regs.map.summary
.........\...\uart_regs.pin
.........\...\uart_regs.pof

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