On VHDL on the DSP s EMIF

write_rd
........\db
........\..\prev_cmp_write_rd.qmsg
........\..\wed.wsf
........\..\write_rd.asm.qmsg
........\..\write_rd.cbx.xml
........\..\write_rd.cmp.cdb
........\..\write_rd.cmp.hdb
........\..\write_rd.cmp.logdb
........\..\write_rd.cmp.rdb
........\..\write_rd.cmp.tdb
........\..\write_rd.cmp0.ddb
........\..\write_rd.dbp
........\..\write_rd.db_info
........\..\write_rd.eco.cdb
........\..\write_rd.eds_overflow
........\..\write_rd.fit.qmsg
........\..\write_rd.fnsim.cdb
........\..\write_rd.fnsim.hdb
........\..\write_rd.fnsim.qmsg
........\..\write_rd.hier_info
........\..\write_rd.hif
........\..\write_rd.map.cdb
........\..\write_rd.map.hdb
........\..\write_rd.map.logdb
........\..\write_rd.map.qmsg
........\..\write_rd.pre_map.cdb
........\..\write_rd.pre_map.hdb
........\..\write_rd.psp
........\..\write_rd.pss
........\..\write_rd.rtlv.hdb
........\..\write_rd.rtlv_sg.cdb
........\..\write_rd.rtlv_sg_swap.cdb
........\..\write_rd.sgdiff.cdb
........\..\write_rd.sgdiff.hdb
........\..\write_rd.sim.cvwf
........\..\write_rd.sim.hdb
........\..\write_rd.sim.qmsg
........\..\write_rd.sim.rdb
........\..\write_rd.simfam
........\..\write_rd.sld_design_entry.sci
........\..\write_rd.sld_design_entry_dsc.sci
........\..\write_rd.syn_hier_info
........\..\write_rd.tan.qmsg
........\..\write_rd.tis_db_list.ddb
........\write_rd.asm.rpt
........\write_rd.bdf
........\write_rd.bsf
........\write_rd.done
........\write_rd.fit.rpt
........\write_rd.fit.summary
........\write_rd.flow.rpt
........\write_rd.map.rpt
........\write_rd.map.summary
........\write_rd.pin
........\write_rd.pof
........\write_rd.qpf
........\write_rd.qsf
........\write_rd.qws
........\write_rd.sim.rpt
........\write_rd.tan.rpt
........\write_rd.tan.summary
........\write_rd.vwf

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