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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 67kb
  • Downloaded :0次
  • Author :张****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Two of the stopwatch button, one is stopped, a reset
Packet file list
(Preview for download)
yh1
...\LIB.DLS
...\U0244969.DLS
...\U5176946.DLS
...\U5497246.DLS
...\watch.acf
...\watch.fit
...\watch.hex
...\watch.hif
...\watch.mmf
...\watch.ndb
...\watch.pin
...\watch.pof
...\watch.rpt
...\watch.snf
...\watch.sof
...\WATCH.sym
...\watch.ttf
...\watch.vhd
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