Embedded_risc IP CORE. VERY GOOD AS A STUDY FILE

embedded_risc
.............\embedded_risc
.............\.............\CVS
.............\.............\...\Entries
.............\.............\...\Repository
.............\.............\...\Root
.............\.............\embedded_risc
.............\.............\.............\CVS
.............\.............\.............\...\Entries
.............\.............\.............\...\Repository
.............\.............\.............\...\Root
.............\.............\Machine_Language
.............\.............\................\CVS
.............\.............\................\...\Entries
.............\.............\................\...\Repository
.............\.............\................\...\Root
.............\.............\................\program.txt
.............\.............\SOC_Design.pdf
.............\.............\Test_Bench_Verilog
.............\.............\..................\CVS
.............\.............\..................\...\Entries
.............\.............\..................\...\Repository
.............\.............\..................\...\Root
.............\.............\..................\Top_level_tb.tf
.............\.............\Verilog
.............\.............\.......\ACC.V
.............\.............\.......\ALU.V
.............\.............\.......\bus_arbiter.v
.............\.............\.......\cmd_ack.v
.............\.............\.......\cmd_decoder.v
.............\.............\.......\cmd_detector.v
.............\.............\.......\cmd_generator.v
.............\.............\.......\cmd_internal_reg.v
.............\.............\.......\command_if.v
.............\.............\.......\CONTROL.V
.............\.............\.......\CVS
.............\.............\.......\...\Entries
.............\.............\.......\...\Repository
.............\.............\.......\...\Root
.............\.............\.......\data_cache_way0.v
.............\.............\.......\data_cache_way1.v
.............\.............\.......\data_cache_way2.v
.............\.............\.......\data_cache_way3.v
.............\.............\.......\data_in_reg.v
.............\.............\.......\data_port.v
.............\.............\.......\dma_cntrl.v
.............\.............\.......\dma_fifo.v
.............\.............\.......\dma_internal_reg.v
.............\.............\.......\flash_ctrl.v
.............\.............\.......\fsm.v
.............\.............\.......\instruction_cache_way0.v
.............\.............\.......\instruction_cache_way1.v
.............\.............\.......\instruction_cache_way2.v
.............\.............\.......\instruction_cache_way3.v
.............\.............\.......\IR.V
.............\.............\.......\k9f1g08u0m.v
.............\.............\.......\lru_data_cache.v
.............\.............\.......\lru_instruction_cache.v
.............\.............\.......\MEM.V
.............\.............\.......\MUX12.V
.............\.............\.......\MUX16.V
.............\.............\.......\oe_generator.v
.............\.............\.......\parameter.v
.............\.............\.......\PC.V
.............\.............\.......\ras_cas_delay.v
.............\.............\.......\ref_ack.v
.............\.............\.......\ref_timer.v
.............\.............\.......\risc.v
.............\.............\.......\sdram.v
.............\.............\.......\sdramctrl_rtl.v
.............\.............\.......\sdram_cntrl.v
.............\.............\.......\sdram_mux.v
.............\.............\.......\sdram_port.v
.............\.............\.......\soc.v
.............\.............\.......\timer.v
.............\.............\.......\uart.v

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