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SHUZIMIAOBIAO

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 6kb
  • Downloaded :0次
  • Author :朱****
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Introduction - If you have any usage issues, please Google them yourself
Stopwatch logical structure is relatively simple, it mainly shows decoder, prescaler, decimal counter, alarm and six counter-band components. Throughout the stopwatch the most critical is how to get an accurate pulse 100Hz time, in addition, a whole also need a stopwatch start signal and a zero signal, in order to be able to start and stop at any time. Stopwatch six output shows that were hundredth of a second, one-tenth of seconds, seconds, 10 seconds, hours, very, so a total of six counters corresponding, 6 all counter-wide code for BCD output, making it easier for At the same time show decoder connections. When the time up to 60 minutes later, the buzzer sound of ringing 10.
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数字秒表.doc
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