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SystemverilogSource

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 486kb
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  • Author :磊**
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Introduction - If you have any usage issues, please Google them yourself
SystemVerilog procedures need friends can see
Packet file list
(Preview for download)
systemverilog程序
.................\fifo_xactn.sv
.................\.............\fifo_xactn.sv
.................\lab1
.................\....\lab1
.................\....\....\hdl
.................\....\....\...\arb.v
.................\....\....\...\arb_if.v
.................\....\....\...\top.v
.................\....\....\Makefile
.................\....\....\tests
.................\....\....\.....\test.v
.................\region
.................\......\region
.................\......\......\Makefile
.................\......\......\README.txt
.................\......\......\region.sv
.................\......\......\sample.sv
.................\SystemVerilog
.................\.............\snug04_bromley_smith
.................\.............\....................\bus_if
.................\.............\....................\......\apb.v
.................\.............\....................\......\apb_assertions.v
.................\.............\....................\......\CORDIC_par_seq_APB.v
.................\.............\....................\......\fail.v
.................\.............\....................\common
.................\.............\....................\......\defs.v
.................\.............\....................\c_model
.................\.............\....................\.......\c_model.c
.................\.............\....................\.......\c_model.v
.................\.............\....................\par_seq
.................\.............\....................\.......\CORDIC_par_seq.v
.................\.............\....................\snug04_bromley_smith_paper.pdf
.................\.............\....................\snug04_bromley_smith_slides.pdf
.................\.............\....................\Testbench
.................\.............\....................\.........\CORDIC_par_seq_APB_modport_tf.v
.................\.............\....................\.........\CORDIC_par_seq_APB_testcase.v
.................\.............\....................\.........\CORDIC_par_seq_APB_test_master.v
.................\.............\....................\.........\CORDIC_par_seq_APB_test_master_RTL.v
.................\VMM_Primers
.................\...........\apb
.................\...........\...\apb.sv
.................\...........\...\apb_if.sv
.................\...........\...\apb_master.sv
.................\...........\...\apb_monitor.sv
.................\...........\...\apb_rw.sv
.................\...........\...\apb_slave.sv
.................\...........\Command_Master_Xactor
.................\...........\.....................\Makefile
.................\...........\.....................\slave_ip.sv
.................\...........\.....................\tb_env.sv
.................\...........\.....................\tb_top.sv
.................\...........\.....................\test_simple.sv
.................\...........\Command_Monitor_Xactor
.................\...........\......................\Makefile
.................\...........\......................\master_ip.sv
.................\...........\......................\slave_ip.sv
.................\...........\......................\tb_env.sv
.................\...........\......................\tb_top.sv
.................\...........\......................\test_annotate.sv
.................\...........\......................\test_simple.sv
.................\...........\Command_Slave_Xactor
.................\...........\....................\Makefile
.................\...........\....................\master_ip.sv
.................\...........\....................\slave_ip.sv
.................\...........\....................\tb_env.sv
.................\...........\....................\tb_top.sv
.................\...........\....................\test_annotate.sv
.................\...........\....................\test_simple.sv
.................\...........\RAL
.................\...........\...\.vcsmx_rebuild
.................\...........\...\apb_rw_xlate.sv
.................\...........\...\dut.sv
.................\...........\...\Makefile
................
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