This is a language with VHDL digital circuit process, learning and reference purposes only.

seg7_b
......\db
......\..\seg7_b.asm.qmsg
......\..\seg7_b.cbx.xml
......\..\seg7_b.cmp.cdb
......\..\seg7_b.cmp.hdb
......\..\seg7_b.cmp.qrpt
......\..\seg7_b.cmp.rdb
......\..\seg7_b.cmp.tdb
......\..\seg7_b.cmp0.ddb
......\..\seg7_b.dbp
......\..\seg7_b.db_info
......\..\seg7_b.eco.cdb
......\..\seg7_b.eds_overflow
......\..\seg7_b.fit.qmsg
......\..\seg7_b.hier_info
......\..\seg7_b.hif
......\..\seg7_b.map.cdb
......\..\seg7_b.map.hdb
......\..\seg7_b.map.qmsg
......\..\seg7_b.pre_map.cdb
......\..\seg7_b.pre_map.hdb
......\..\seg7_b.psp
......\..\seg7_b.rpp.qmsg
......\..\seg7_b.rtlv.hdb
......\..\seg7_b.rtlv_sg.cdb
......\..\seg7_b.rtlv_sg_swap.cdb
......\..\seg7_b.sgate.rvd
......\..\seg7_b.sgate_sm.rvd
......\..\seg7_b.sgdiff.cdb
......\..\seg7_b.sgdiff.hdb
......\..\seg7_b.sim.hdb
......\..\seg7_b.sim.qmsg
......\..\seg7_b.sim.qrpt
......\..\seg7_b.sim.rdb
......\..\seg7_b.sim.vwf
......\..\seg7_b.sld_design_entry.sci
......\..\seg7_b.sld_design_entry_dsc.sci
......\..\seg7_b.syn_hier_info
......\..\seg7_b.tan.qmsg
......\seg7_b.asm.rpt
......\seg7_b.done
......\seg7_b.fit.eqn
......\seg7_b.fit.rpt
......\seg7_b.fit.summary
......\seg7_b.flow.rpt
......\seg7_b.map.eqn
......\seg7_b.map.rpt
......\seg7_b.map.summary
......\seg7_b.pin
......\seg7_b.pof
......\seg7_b.qpf
......\seg7_b.qsf
......\seg7_b.qws
......\seg7_b.sim.rpt
......\seg7_b.tan.rpt
......\seg7_b.tan.summary
......\seg7_b.vhd
......\seg7_b.vwf
......\Vhdl1.vhd

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