Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

shuzizhongdianlu

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 1kb
  • Downloaded :0次
  • Author :lin***
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Download1 Download2
Don't use download software fo downloading.
If download fail,Try it again for free.
Introduction - If you have any usage issues, please Google them yourself
The use of counters and prescaler design a real-time clock. Mold needs a total of 24 counters, 2 Die 6 counters, two-mode 10 counters, a generation of 1Hz the divider and six digital tube decoder. End-users HEX5 ~ HEX4 show hours (0 ~ 23), with HEX3 ~ HEX2 show minutes (0 ~ 59), with HEX1 ~ HEX0 showed seconds (0 ~ 59).
Packet file list
(Preview for download)
shuzizhongdianlu.txt
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is one of the largest source code repositories on the Internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.