This procedure is used VHDL language, including the parallel port communication, DDS motor, encoder signal processing and so on, to look at this area of engineering staff have a certain reference

dp_test
.......\db
.......\..\add_sub_0nh.tdf
.......\..\dp_test.asm.qmsg
.......\..\dp_test.asm_labs.ddb
.......\..\dp_test.cbx.xml
.......\..\dp_test.cmp.cdb
.......\..\dp_test.cmp.hdb
.......\..\dp_test.cmp.qrpt
.......\..\dp_test.cmp.rdb
.......\..\dp_test.cmp.tdb
.......\..\dp_test.cmp0.ddb
.......\..\dp_test.dbp
.......\..\dp_test.db_info
.......\..\dp_test.eco.cdb
.......\..\dp_test.eds_overflow
.......\..\dp_test.fit.qmsg
.......\..\dp_test.fnsim.hdb
.......\..\dp_test.fnsim.qmsg
.......\..\dp_test.hier_info
.......\..\dp_test.hif
.......\..\dp_test.map.cdb
.......\..\dp_test.map.hdb
.......\..\dp_test.map.qmsg
.......\..\dp_test.pre_map.cdb
.......\..\dp_test.pre_map.hdb
.......\..\dp_test.psp
.......\..\dp_test.rtlv.hdb
.......\..\dp_test.rtlv_sg.cdb
.......\..\dp_test.rtlv_sg_swap.cdb
.......\..\dp_test.sgdiff.cdb
.......\..\dp_test.sgdiff.hdb
.......\..\dp_test.signalprobe.cdb
.......\..\dp_test.sim.hdb
.......\..\dp_test.sim.qmsg
.......\..\dp_test.sim.qrpt
.......\..\dp_test.sim.rdb
.......\..\dp_test.sim.vwf
.......\..\dp_test.sld_design_entry.sci
.......\..\dp_test.sld_design_entry_dsc.sci
.......\..\dp_test.syn_hier_info
.......\..\dp_test.tan.qmsg
.......\dp_test.asm.rpt
.......\dp_test.bsf
.......\dp_test.cdf
.......\dp_test.done
.......\dp_test.dpf
.......\dp_test.fit.eqn
.......\dp_test.fit.rpt
.......\dp_test.fit.summary
.......\dp_test.fld
.......\dp_test.flow.rpt
.......\dp_test.map.eqn
.......\dp_test.map.rpt
.......\dp_test.map.summary
.......\dp_test.pin
.......\dp_test.pof
.......\dp_test.qpf
.......\dp_test.qsf
.......\dp_test.qws
.......\dp_test.sim.rpt
.......\dp_test.tan.rpt
.......\dp_test.tan.summary
.......\dp_test.tcl
.......\dp_test.vhd
.......\dp_test.vwf
.......\serv_req_info.txt

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