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watchver

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 143kb
  • Downloaded :0次
  • Author :jin****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
The clock to prepare a VHDL process, all source code packaged Upload
Packet file list
(Preview for download)
watchver
........\cnt60.v
........\core.tpl
........\dcm1.v
........\dcm1.xaw
........\dcm1_arwz.ucf
........\decode.v
........\hex2led.v
........\readme
........\smallcntr.v
........\statmach.v
........\stopwatch.v
........\stopwatch.vcd
........\stopwatch_tb.tf
........\stopwatch_tb.v
........\stopwatch_tb_timing.tf
........\tenths.edn
........\tenths.v
........\tenths.veo
........\tenths.xco
........\watch_ver.ise
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