Here the design of commonly used modules have EDA source code, FFT, DDS PS2_keyboard, VGA and so on, have places on the FPGA reference yourself

EDA实验中用到的常用模块
.......................\Verilog版本
.......................\...........\ASCII
.......................\...........\.....\ASCII.hex
.......................\...........\correlator_test
.......................\...........\...............\correlator_test.bsf
.......................\...........\...............\correlator_test.v
.......................\...........\crc5_test
.......................\...........\.........\crc5_test.bsf
.......................\...........\.........\crc5_test.v
.......................\...........\dac_test
.......................\...........\........\dac_test.bsf
.......................\...........\........\dac_test.v
.......................\...........\dds_rom
.......................\...........\.......\dds_rom.mif
.......................\...........\dds_test
.......................\...........\........\dds_test.v
.......................\...........\fft_test
.......................\...........\........\for QuickEDA
.......................\...........\........\............\fft_test.tcl
.......................\...........\........\for QuickSOPC-1C12
.......................\...........\........\..................\fft_test.tcl
.......................\...........\........\for QuickSOPC-1C6
.......................\...........\........\.................\fft_test.tcl
.......................\...........\filter_200us
.......................\...........\............\filter_200us.bsf
.......................\...........\............\filter_200us.v
.......................\...........\image
.......................\...........\.....\image.hex
.......................\...........\int_div
.......................\...........\.......\int_div.bsf
.......................\...........\.......\int_div.v
.......................\...........\key_led
.......................\...........\.......\key_led.bsf
.......................\...........\.......\key_led.v
.......................\...........\logic_synsz
.......................\...........\...........\for QuickEDA
.......................\...........\...........\............\logic_synsz.tcl
.......................\...........\...........\for QuickSOPC-1C12
.......................\...........\...........\..................\logic_synsz.tcl
.......................\...........\...........\for QuickSOPC-1C6
.......................\...........\...........\.................\logic_synsz.tcl
.......................\...........\logo
.......................\...........\....\logo.hex
.......................\...........\moto_test
.......................\...........\.........\moto_test.bsf
.......................\...........\.........\moto_test.v
.......................\...........\mouse_ico
.......................\...........\.........\mouse_ico.hex
.......................\...........\ps2_keyboard_test
.......................\...........\.................\for QuickEDA
.......................\...........\.................\............\ps2_keyboard_test.tcl
.......................\...........\.................\for QuickSOPC-1C12
.......................\...........\.................\..................\ps2_keyboard_test.tcl
.......................\...........\.................\for QuickSOPC-1C6
.......................\...........\.................\.................\ps2_keyboard_test.tcl
.......................\...........\ps2_mouse_test
.......................\...........\..............\for QuickEDA
.......................\...........\..............\............\ps2_mouse_test.tcl
.......................\...........\..............\for QuickSOPC-1C12
.......................\...........\..............\..................\ps2_mouse_test.tcl
.......................\...........\..............\for QuickSOPC-1C6
.......................\...........\..............\.................\ps2_mouse_test.tcl
.......................\...........\schk_test
.......................\...........\.........\schk_test.bsf
.......................\...........\.........\schk_test.v
.......................\...........\sine
.......................\...........\....\sine.mif
.......................\.......

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