Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the sub-circuits can be used as smaller benchmarks.

stereo_vision
.............\basic_type.vhd
.............\combine_res.vhd
.............\corr.vhd
.............\corr_seq.vhd
.............\fifo.vhd
.............\find_max.vhd
.............\fltr_compute_f1.vhd
.............\fltr_compute_f2.vhd
.............\fltr_compute_f3.vhd
.............\fltr_compute_h1.vhd
.............\fltr_compute_h2.vhd
.............\fltr_compute_h3.vhd
.............\fltr_compute_h4.vhd
.............\h_fltr.vhd
.............\lp_fltr.vhd
.............\lp_fltr_v1.vhd
.............\lp_fltr_v2.vhd
.............\lp_fltr_v4.vhd
.............\mult_const_f1_2.edn
.............\mult_const_f1_3.edn
.............\mult_const_f1_4.edn
.............\mult_const_f1_5.edn
.............\mult_const_f2_2.edn
.............\mult_const_f2_3.edn
.............\mult_const_f2_4.edn
.............\mult_const_f2_5.edn
.............\mult_const_f3_2.edn
.............\mult_const_f3_3.edn
.............\mult_const_f3_4.edn
.............\mult_const_f3_5.edn
.............\mult_const_f3_6.edn
.............\mult_const_f3_7.edn
.............\mult_const_f3_8.edn
.............\mult_const_h1_2.edn
.............\mult_const_h1_3.edn
.............\mult_const_h1_4.edn
.............\mult_const_h1_5.edn
.............\mult_const_h1_6.edn
.............\mult_const_h1_7.edn
.............\mult_const_h1_8.edn
.............\mult_const_h2_2.edn
.............\mult_const_h2_3.edn
.............\mult_const_h2_4.edn
.............\mult_const_h2_5.edn
.............\mult_const_h3_2.edn
.............\mult_const_h3_3.edn
.............\mult_const_h3_4.edn
.............\mult_const_h3_5.edn
.............\mult_const_h3_6.edn
.............\mult_const_h3_7.edn
.............\mult_const_h3_8.edn
.............\mult_const_h4_2.edn
.............\mult_const_h4_3.edn
.............\mult_const_h4_4.edn
.............\mult_const_h4_5.edn
.............\my_div_16.edn
.............\my_div_16_slow.edn
.............\my_fifo.edn
.............\my_fifo_1.edn
.............\my_fifo_179.edn
.............\my_fifo_2.edn
.............\my_fifo_316.edn
.............\my_fifo_359.edn
.............\my_fifo_496.edn
.............\my_fifo_89.edn
.............\my_fir_f1.edn
.............\my_fir_f2.edn
.............\my_fir_f3.edn
.............\my_fir_h1.edn
.............\my_fir_h2.edn
.............\my_fir_h3.edn
.............\my_fir_h4.edn
.............\my_mult_8.edn
.............\my_mult_8_slow.edn
.............\my_ram.edn
.............\port_bus_1to0.vhd
.............\port_bus_1to0_1.vhd
.............\port_bus_2to1.vhd
.............\port_bus_2to1_1.vhd
.............\quadintr_10_20.vhd
.............\quadintr_5_20.vhd
.............\README.pdf
.............\scaler.vhd
.............\scl_h_fltr.vhd
.............\scl_v_fltr.vhd
.............\sh_reg.vhd
.............\sh_reg_1.vhd
.............\steer_fltr.vhd
.............\sv_chip0.vhd
.............\sv_chip1.vhd
.............\sv_chip2.vhd
.............\sv_chip3.vhd
.............\v_fltr.vhd
.............\v_fltr_316.vhd
.............\v_fltr_496.vhd
.............\wrapper_corr_10.vhd
.............\wrapper_corr_20.vhd
.............\wrapper_corr_5_seq.vhd
.............\wrapper_norm.vhd

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