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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 18kb
  • Downloaded :0次
  • Author :Nira*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
vhdl codes for combinational and sequential circuit
Packet file list
(Preview for download)
vhdl
....\And_gate.vhd
....\count6.vhd
....\Counter.vhd
....\Counter_tb.vhd
....\end sem
....\.......\adder_full.vhd
....\.......\end sem.cr.mti
....\.......\ieee
....\.......\....\_info
....\.......\modelsim.ini
....\JKFF.vhd
....\JKFF_tb.vhd
....\Shift register.vhd
....\work
....\....\counter
....\....\.......\bhv.asm
....\....\.......\bhv.dat
....\....\.......\_primary.dat
....\....\counter_tb
....\....\..........\bhv.asm
....\....\..........\bhv.dat
....\....\..........\_primary.dat
....\....\jkff
....\....\....\bhv.asm
....\....\....\bhv.dat
....\....\....\_primary.dat
....\....\jkff_tb
....\....\.......\bhv.asm
....\....\.......\bhv.dat
....\....\.......\_primary.dat
....\....\shiftreg
....\....\........\bhv.asm
....\....\........\bhv.dat
....\....\........\_primary.dat
....\....\_info
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