FPGA implementation and the host computer' s serial communication, which by the baud rate generator, shift register, counters, detecter, switch, switch_bus such as function blocks integrated together.

UART_SUCCESS
............\baudrate_generator.bsf
............\baudrate_generator.vhd
............\baudrate_generator.vwf
............\counter.bsf
............\counter.vhd
............\db
............\..\altsyncram_9mi2.tdf
............\..\altsyncram_jji2.tdf
............\..\altsyncram_nji2.tdf
............\..\cmpr_5mh.tdf
............\..\cmpr_7mh.tdf
............\..\cmpr_fnh.tdf
............\..\cntr_5hi.tdf
............\..\cntr_68j.tdf
............\..\cntr_78i.tdf
............\..\cntr_7hi.tdf
............\..\cntr_88j.tdf
............\..\cntr_cfh.tdf
............\..\cntr_dfh.tdf
............\..\cntr_fii.tdf
............\..\cntr_g5i.tdf
............\..\cntr_g9j.tdf
............\..\cntr_h5i.tdf
............\..\cntr_hek.tdf
............\..\cntr_qbk.tdf
............\..\cntr_rbk.tdf
............\..\decode_ogi.tdf
............\..\uart_top.asm.qmsg
............\..\uart_top.atom.rvd
............\..\uart_top.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
............\..\uart_top.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb
............\..\uart_top.cbx.xml
............\..\uart_top.cmp.bpm
............\..\uart_top.cmp.cdb
............\..\uart_top.cmp.ecobp
............\..\uart_top.cmp.hdb
............\..\uart_top.cmp.logdb
............\..\uart_top.cmp.rdb
............\..\uart_top.cmp.tdb
............\..\uart_top.cmp0.ddb
............\..\uart_top.cmp_bb.cdb
............\..\uart_top.cmp_bb.hdb
............\..\uart_top.cmp_bb.logdb
............\..\uart_top.cmp_bb.rcf
............\..\uart_top.dbp
............\..\uart_top.db_info
............\..\uart_top.eco.cdb
............\..\uart_top.eds_overflow
............\..\uart_top.fit.qmsg
............\..\uart_top.hier_info
............\..\uart_top.hif
............\..\uart_top.map.bpm
............\..\uart_top.map.cdb
............\..\uart_top.map.ecobp
............\..\uart_top.map.hdb
............\..\uart_top.map.logdb
............\..\uart_top.map.qmsg
............\..\uart_top.map_bb.cdb
............\..\uart_top.map_bb.hdb
............\..\uart_top.map_bb.logdb
............\..\uart_top.merge.qmsg
............\..\uart_top.pre_map.cdb
............\..\uart_top.pre_map.hdb
............\..\uart_top.psp
............\..\uart_top.pss
............\..\uart_top.rpp.qmsg
............\..\uart_top.rtlv.hdb
............\..\uart_top.rtlv_sg.cdb
............\..\uart_top.rtlv_sg_swap.cdb
............\..\uart_top.sgate.rvd
............\..\uart_top.sgate_sm.rvd
............\..\uart_top.sgdiff.cdb
............\..\uart_top.sgdiff.hdb
............\..\uart_top.signalprobe.cdb
............\..\uart_top.sim.hdb
............\..\uart_top.sim.qmsg
............\..\uart_top.sim_temp_.vwf
............\..\uart_top.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
............\..\uart_top.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb
............\..\uart_top.sld_design_entry.sci
............\..\uart_top.sld_design_entry_dsc.sci
............\..\uart_top.smp_dump.txt
............\..\uart_top.syn_hier_info
............\..\uart_top.tan.qmsg
............\..\wed.wsf
............\detector.bsf
............\detector.vhd
............\parity_verifier.bsf
............\parity_verifier.vhd
............\shift_register.bsf
............\shift_register.vhd
............\stp1.stp
............\switch.bsf
............\switch.vhd
............\switch_bus.bsf
............\switch_bus.vhd
............\uart_core.bsf
............\uart_core.vhd
............\UART_PACKAGE.vhd

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