Verilog study some of the information. Pulse width modulation control are the subject, as well as the source code and simulation files. Feel good style of code, you can study about.

pre_sim
.......\modelsim.ini
.......\source
.......\......\tb_pwm_ctl.v
.......\......\test6.v
.......\tb_pwm_ctl
.......\..........\verilog.asm
.......\..........\_primary.dat
.......\..........\_primary.vhd
.......\test6
.......\.....\verilog.asm
.......\.....\_primary.dat
.......\.....\_primary.vhd
.......\vsim.wlf
.......\wave.do
.......\_info
Verilog 课程上机考题.doc

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