FPGA serial modules, FPGA implementation with the PC-Serial communication.

uart
....\baud.bsf
....\baud.vhd
....\baud.vhd.bak
....\db
....\..\add_sub_soh.tdf
....\..\prev_cmp_uart.asm.qmsg
....\..\prev_cmp_uart.fit.qmsg
....\..\prev_cmp_uart.map.qmsg
....\..\prev_cmp_uart.qmsg
....\..\prev_cmp_uart.tan.qmsg
....\..\uart.asm.qmsg
....\..\uart.cbx.xml
....\..\uart.cmp.cdb
....\..\uart.cmp.hdb
....\..\uart.cmp.logdb
....\..\uart.cmp.rdb
....\..\uart.cmp.tdb
....\..\uart.cmp0.ddb
....\..\uart.dbp
....\..\uart.db_info
....\..\uart.eco.cdb
....\..\uart.eds_overflow
....\..\uart.fit.qmsg
....\..\uart.hier_info
....\..\uart.hif
....\..\uart.map.cdb
....\..\uart.map.hdb
....\..\uart.map.logdb
....\..\uart.map.qmsg
....\..\uart.pre_map.cdb
....\..\uart.pre_map.hdb
....\..\uart.psp
....\..\uart.pss
....\..\uart.rtlv.hdb
....\..\uart.rtlv_sg.cdb
....\..\uart.rtlv_sg_swap.cdb
....\..\uart.sgdiff.cdb
....\..\uart.sgdiff.hdb
....\..\uart.sim.cvwf
....\..\uart.sim.hdb
....\..\uart.sim.qmsg
....\..\uart.sim.rdb
....\..\uart.sld_design_entry.sci
....\..\uart.sld_design_entry_dsc.sci
....\..\uart.smp_dump.txt
....\..\uart.syn_hier_info
....\..\uart.tan.qmsg
....\..\uart.tis_db_list.ddb
....\..\wed.wsf
....\reciever.bsf
....\reciever.vhd
....\sopc_builder_log.txt
....\transfer.bsf
....\transfer.vhd
....\transfer.vhd.bak
....\uart.asm.rpt
....\uart.bdf
....\uart.done
....\uart.dpf
....\uart.fit.rpt
....\uart.fit.summary
....\uart.flow.rpt
....\uart.map.rpt
....\uart.map.summary
....\uart.pin
....\uart.pof
....\uart.qpf
....\uart.qsf
....\uart.qws
....\uart.sim.rpt
....\uart.sof
....\uart.tan.rpt
....\uart.tan.summary
....\uart.vwf

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