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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 115kb
  • Downloaded :0次
  • Author :chuj****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Does the input clock frequency divided by 8 and divided by the number of sub-4 sub-frequency function
Packet file list
(Preview for download)
cnt
...\cmp_state.ini
...\CNT2.asm.rpt
...\CNT2.bsf
...\CNT2.done
...\CNT2.fit.eqn
...\CNT2.fit.rpt
...\CNT2.flow.rpt
...\CNT2.map.eqn
...\CNT2.map.rpt
...\CNT2.pin
...\CNT2.pof
...\CNT2.qpf
...\CNT2.qsf
...\CNT2.qws
...\CNT2.sim.rpt
...\CNT2.sof
...\CNT2.tan.rpt
...\CNT2.tan.summary
...\CNT2.vhd
...\CNT2.vwf
...\db
...\..\CNT2-sim.vwf
...\..\CNT2.asm.qmsg
...\..\CNT2.cmp.cdb
...\..\CNT2.cmp.ddb
...\..\CNT2.cmp.hdb
...\..\CNT2.cmp.rdb
...\..\CNT2.cmp.tdb
...\..\CNT2.csf.qmsg
...\..\CNT2.db_info
...\..\CNT2.fit.qmsg
...\..\CNT2.hif
...\..\CNT2.icc
...\..\CNT2.map.cdb
...\..\CNT2.map.hdb
...\..\CNT2.map.qmsg
...\..\CNT2.pre_map.hdb
...\..\CNT2.project.hdb
...\..\CNT2.rtlv.hdb
...\..\CNT2.rtlv_sg.cdb
...\..\CNT2.rtlv_sg_swap.cdb
...\..\CNT2.sgdiff.cdb
...\..\CNT2.sgdiff.hdb
...\..\CNT2.signalprobe.cdb
...\..\CNT2.sim.hdb
...\..\CNT2.sim.qmsg
...\..\CNT2.sim.rdb
...\..\CNT2.tan.qmsg
...\..\CNT2_cmp.qrpt
...\..\CNT2_hier_info
...\..\CNT2_sim.qrpt
...\..\CNT2_syn_hier_info
...\sim.cfg
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